Parallel Processor with Dynamic SIMD Controller Allocation
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Solution Overview
Problem
Existing SIMD architectures face limitations in throughput efficiency due to hardwired processing elements and overlapping communication channels, which restrict scalability and flexibility, especially when handling multiple instruction streams and data processing tasks.
Innovation Solution
A parallel processor with dynamically configurable SIMD controllers that can connect to varying numbers of data processing units based on processing tasks, allowing for real-time allocation and non-overlapping subgroups to enhance processing efficiency and flexibility, eliminating the need for additional components like routers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If processing elements are hardwired to have specific predetermined relationships with controllers, then device complexity is reduced, but adaptability and versatility deteriorate
Solution Approach 1:
The patent implements dynamic reconfigurability where processing elements can be selectively activated and deactivated based on task requirements. The controller can dynamically form different groups of PEs for different processing tasks, transforming the static hardwired architecture into a dynamic reconfigurable system that adapts to various computational needs without increasing physical complexity
2Productivity
If overlapping communication channels are used, then throughput is improved, but device complexity increases due to coordination requirements
Solution Approach 1:
The patent segments the communication channels into distinct non-overlapping paths between controllers and processing element groups. Each controller has dedicated communication channels to its assigned PE group, eliminating the need for complex coordination of overlapping channels while maintaining efficient data flow for parallel processing operations
3Adaptability or versatility
If additional components like routers are added to handle communication across non-adjacent processing elements, then adaptability improves, but device complexity and power consumption increase
Solution Approach 1:
The patent makes adjacent processing elements multi-functional by enabling them to handle both local and remote data communication tasks. Through selective activation and group formation, adjacent PEs can effectively communicate with and process data from non-adjacent elements without requiring dedicated router components, achieving universal communication capability within the PE array
4Adaptability or versatility
If a plurality of processors are implemented in parallel to handle multiple instruction streams, then adaptability improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent merges multiple processor functionalities into a single reconfigurable processor system. By dynamically forming different groups of processing elements under different controller management, the system can handle multiple instruction streams simultaneously using shared hardware resources, eliminating the need for multiple separate processor implementations
Data Source
AI summary
A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.