Parallel PWM Generation via FIFO and Serializer Circuit
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Solution Overview
Problem
Existing PWM circuit implementations are inflexible and limited by a counter operating at a clock frequency based on the minimum pulse width, restricting the maximum frequency of the PWM output signal and making it difficult to generate signals for different protocols.
Innovation Solution
A system comprising a control circuit, a FIFO circuit, and a serializer circuit that generates parallel PWM signals, which are then converted to serial PWM data, allowing for higher data rates and reduced clock frequency requirements, enabling operation at lower frequencies and flexibility in generating PWM signals for various protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a counter operates at a clock frequency based on the minimum pulse width, then the PWM signal can be generated with the required minimum pulse width, but the maximum frequency of the PWM output signal is restricted
Solution Approach 1:
The patent divides the PWM generation process into two independent parts: a control circuit that generates parallel PWM data at a lower clock frequency, and a serializer circuit that converts parallel data to serial output at the higher PWM frequency. This segmentation allows each circuit to operate at its own optimal frequency without being constrained by the other, thereby resolving the contradiction between achieving high PWM output frequency and maintaining manageable device complexity.
Solution Approach 2:
The patent introduces parallel PWM data as an intermediary between the control circuit and the serializer circuit. The control circuit generates parallel PWM data representing duty cycle information at a lower frequency, which is then fed to the serializer circuit. This intermediary allows the control circuit to operate at a manageable clock frequency while the serializer generates the high-frequency serial PWM output signal.
2Speed
If the control circuit operates at a higher clock frequency to generate high-frequency PWM signals, then the maximum PWM output frequency increases, but the timing requirements become more stringent and difficult to meet
Solution Approach 1:
By segmenting the PWM generation into parallel data generation at low frequency and serial conversion at high frequency, the patent allows the control circuit to operate with relaxed timing requirements while the serializer handles the high-frequency timing-critical operations. This division of labor resolves the contradiction between high PWM frequency and ease of operation.
Solution Approach 2:
The patent transitions from a single-dimensional approach (single clock frequency for all PWM operations) to a two-dimensional approach by introducing parallel data paths. The parallel PWM data dimension allows duty cycle information to be prepared at low frequency, while the serial output dimension handles high-frequency transmission, thereby easing timing constraints on the control circuit.
3Adaptability or versatility
If a counter-based PWM circuit is used, then PWM signals can be generated, but the circuit is not flexible enough to generate PWM signals for different protocols
Solution Approach 1:
The patent implements a dynamic and reconfigurable control circuit that can be programmed via software or configuration data to generate parallel PWM data according to different PWM protocols. This dynamic capability allows the same hardware architecture to adapt to various protocols (such as I2C, SPI, or custom protocols) by changing the control logic, thereby achieving high adaptability without increasing physical device complexity.
Solution Approach 2:
The patent creates a universal PWM generation architecture where the control circuit can serve multiple functions by generating parallel PWM data for different protocols. The same basic structure supports various PWM protocols through software or configuration programming, making the circuit multi-functional and highly adaptable without requiring separate dedicated circuits for each protocol.
Data Source
AI summary
An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in first-out circuit stores the parallel pulse-width modulation data indicated by the first parallel pulse-width modulation signals. The first-in first-out circuit outputs the stored parallel pulse-width modulation data in second parallel pulse-width modulation signals. The serializer circuit converts the parallel pulse-width modulation data indicated by the second parallel pulse-width modulation signals to serial pulse-width modulation data in a serial pulse-width modulation signal.