Parallel Ramp Signal Circuit for Fine Timing at Lower Clock Rates
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Solution Overview
Problem
Existing electronic circuits struggle to provide digital signals with precise ramps at high frequencies using a clock signal with lower frequency, limiting their ability to modify the succession of ramps effectively.
Innovation Solution
An electronic circuit that stores start values, slopes, and duration data for each ramp in memories, using interpolation circuits to generate multiple digital values per clock cycle, allowing for parallel reading and interpolation to achieve the desired ramp succession.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an electronic circuit is clocked by a clock signal at a frequency lower than the desired granularity of the digital signal, then the circuit complexity is reduced, but the temporal accuracy and frequency of the digital signal are insufficient
Solution Approach 1:
The patent divides the generation of digital signal values into multiple parallel interpolation circuits (Nout circuits), each handling a portion of the calculation. This segmentation allows the circuit to achieve high temporal accuracy by generating multiple digital values per clock cycle while distributing the computational complexity across multiple specialized units rather than requiring a single complex high-frequency clocking system.
Solution Approach 2:
The patent transitions from a time-based solution (using a high-frequency clock signal) to a spatial solution (using multiple parallel interpolation circuits operating at a lower clock frequency). By processing Nout digital values simultaneously in parallel circuits within each clock cycle, the system achieves the equivalent of a higher frequency operation without requiring a higher frequency clock, thus resolving the contradiction between temporal accuracy and circuit complexity.
2Productivity
If the circuit generates multiple digital values per clock cycle in parallel, then the temporal accuracy and frequency of the digital signal are improved, but the device complexity increases
Solution Approach 1:
The patent segments the digital signal generation task into Nout independent interpolation circuits, each capable of generating a digital value independently in parallel. This segmentation enables the circuit to produce Nout digital values per clock cycle, significantly increasing productivity. The complexity is managed by using identical, standardized circuit blocks rather than a single complex sequential generator.
Solution Approach 2:
The patent uses memories to pre-store the parameters needed for generating digital signal values (such as ramp characteristics, timing information, and control data). By having this data prepared and stored in advance in the memories, the interpolation circuits can directly compute multiple digital values in parallel without requiring complex real-time data preparation logic, thus increasing productivity while controlling complexity.
3Productivity
If the circuit uses parallel interpolation circuits to generate multiple digital values per clock cycle, then the productivity is improved, but the ease of operation for modifying ramp sequences is reduced
Solution Approach 1:
The patent implements a universal memory structure and control logic that can accommodate different ramp configurations and parameters. The memories store generalized data structures that can represent various ramp types (linear, exponential, custom waveforms) and the interpolation circuits use a unified algorithm to process them. This multi-functionality allows flexible modification of ramp sequences without requiring changes to the underlying circuit architecture, maintaining ease of operation despite high productivity.
Solution Approach 2:
The patent prepares all necessary ramp parameters and control data in advance and stores them in memories before the signal generation begins. By having the complete ramp sequence pre-configured in the memories, users can modify ramp sequences by simply updating the stored data without touching the circuit logic. This preliminary preparation of data separates the flexibility requirement from the processing complexity, allowing easy modification while maintaining high productivity through parallel processing.
Data Source
AI summary
The present description concerns an electronic circuit (10) for providing a digital signal (Sn) comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of digital values of the digital signal at each cycle of the clock signal, Nout being greater than 1. The electronic circuit comprises a first memory (30) in which are stored, for each ramp, first data, and a second memory (32) in which are stored second data relative to the numbers of cycles of the clock signal over which some of the ramps extend, and a first circuit (40) configured to read from the first memory the first data relative to a plurality of successive ramps and from the second memory the second data associated with said plurality of successive ramps, and to supply said digital values.