Parallel Range Code Decoding Circuit for Faster Decompression
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Solution Overview
Problem
The existing range code decoding process in storage systems is slow due to the inability to perform parallel multiplication and table reference for multiple bits, leading to low decompression performance and increased read response times.
Innovation Solution
A decompression circuit that calculates candidate bit values for each bit of an N-bit string based on possible bit histories and selects the correct bit value, allowing for parallel processing to speed up the decoding of range codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If range code decoding is performed using traditional sequential multiplication and table reference methods, then decoding accuracy is maintained, but decoding speed becomes very slow
Solution Approach 1:
The decoding process is segmented into multiple parallel processing paths, where multiple bits are decoded simultaneously through separate multiplication and table reference operations. Each path handles a specific bit position with its own set of registers and logic units, enabling parallel execution while maintaining individual decoding accuracy.
Solution Approach 2:
The invention transitions from sequential single-bit processing to parallel multi-bit processing by adding a dimensional aspect of parallelism. Multiple decoding operations that were previously executed one after another are now executed simultaneously across multiple processing units, effectively moving from a 1D sequential process to a 2D parallel architecture.
2Quantity of substance
If compression ratio is increased using LZMA algorithm with range code, then storage capacity efficiency improves, but read response time increases due to slow decompression
Solution Approach 1:
The decompression circuit performs preliminary parallel preparation of candidate values and probability calculations before final bit selection. By pre-computing multiple potential decoding paths in parallel and then selecting the correct one, the system reduces the critical path delay and accelerates the overall decompression process while maintaining high compression ratios.
3Productivity
If multiplication is performed sequentially for each bit in range code decoding, then circuit complexity is reduced, but processing performance deteriorates
Solution Approach 1:
Multiple multiplication operations for different bit positions are merged into a single parallel processing stage. The circuit combines several multiplication units that operate simultaneously on different bits, allowing the processing of multiple bits in one clock cycle. This merging of operations increases productivity while the modular design keeps circuit complexity manageable.
Data Source
AI summary
To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.