Parallel Raster Image Processing for High-Speed Print Data Synthesis
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Solution Overview
Problem
Existing raster graphics processors are inefficient and costly, requiring serial processing and significant memory resources, which limits flexibility and scalability in converting object-based data to pixel data for high-resolution, high-speed printing applications like single-pass inkjet printers.
Innovation Solution
A raster graphics processor with programmable system-on-chip (PSoC) and multiple processors, capable of parallel processing and converting object-based data into pixel data using vector-based arithmetic logic units, enabling efficient and cost-effective data conversion with low energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial processing is used in raster graphics processors, then device complexity is reduced, but productivity deteriorates due to slow conversion speed
Solution Approach 1:
The patent divides the rasterization task into multiple segments processed by different processing elements simultaneously. The system uses a array of processing elements that can operate in parallel on different portions of the vector graphic data, effectively segmenting the work to achieve high-speed conversion without requiring overly complex sequential processing architectures.
Solution Approach 2:
The patent implements a dynamic processing architecture where processing elements can be selectively activated based on the complexity and type of vector operations required. The system dynamically allocates processing resources to match the workload, allowing simple operations to use fewer resources while complex operations utilize the full parallel processing capability, thus avoiding the need for permanently complex hardware.
2Manufacturing precision
If high memory capacity is provided for rasterization, then manufacturing precision is improved, but loss of substance increases due to large storage requirements
Solution Approach 1:
The patent performs preliminary processing of vector graphic data to identify and pre-calculate rasterization parameters before the actual rasterization occurs. By pre-processing the data to determine which areas require high resolution and what processing intensity is needed, the system can allocate memory resources more efficiently, storing only the necessary data at the required resolution rather than maintaining large buffers for all possible scenarios.
Solution Approach 2:
The patent dynamically adjusts processing and storage parameters based on the characteristics of the vector graphic being processed. The system changes resolution levels, data format, and memory allocation based on the complexity of the vector operations required, allowing high precision when needed while minimizing memory usage for simpler tasks, thus reducing overall storage requirements while maintaining print quality.
Data Source
AI summary
The invention relates to a method, preferably a computer-implemented method, for synthesising m-bit print data and for providing the data to a printer, the method comprising: a) inputting object-based data of at least one image in the form of a page description language into a raster image processor having at least one system-on-chip comprising a plurality of processors; b) converting the object-based data into n-bit pixel data of each colour channel of a first target colour space with a predefined image resolution by providing the object-based data to some or to all of the plurality of processors and processing the data in parallel by means of the processors; c) converting the n-bit pixel data of each colour channel into m-bit print data of each colour channel of a second target colour space by means of at least one dithering algorithm and storing or buffering the m-bit print data in an output memory; d) providing the m-bit print data to the printer and printing on at least one print medium by means of the printer. The system-on-chip is provided as a programmable system-on-chip and the processors are provided as single-instruction-multiple-data-capable or multiple-instruction-multiple-data-capable processors each having at least one vector-based arithmetic logic unit, which vector-based arithmetic logic units have each been configured in such a way that, during the parallel processing according to step b), a plurality of object-based data entering the relevant arithmetic logic unit in parallel, each having a bit width of x-bit, is converted using a predefined set of arithmetic operations into pixel data having a bit width of y-bit, which is greater than the bit width of x-bit, wherein subsequently the y-bit pixel data in the form of a pixel matrix consisting of an integer number of n-bit pixel data is stored or buffered in a pixel memory.