Memory Chip Duty-Ratio Calibration During Parallel Data Read
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Solution Overview
Problem
Existing semiconductor storage devices and memory systems face challenges in calibrating output signals due to variations in duty ratio after power supply activation, which can affect performance and require dedicated circuits like PLL or DLL, potentially deteriorating system efficiency.
Innovation Solution
A memory system with a controller that calibrates the duty ratio of output signals in parallel with data read operations from other chips, using a correction circuit and detection circuit to adjust the duty ratio of signals RE and /RE, allowing for calibration without dedicated circuits like PLL or DLL, thereby maintaining system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated circuits like PLL or DLL are used to calibrate duty ratio, then calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts the duty ratio calibration function from dedicated circuits and implements it using existing memory cells and control logic. The calibration operation is performed by controlling memory cell arrays to generate calibration data that reflects duty ratio variations, eliminating the need for separate PLL or DLL circuits while maintaining calibration accuracy.
Solution Approach 2:
The patent makes existing memory cells serve dual purposes: normal data storage and duty ratio calibration. The same memory cell arrays used for storing user data are also utilized to generate calibration data by controlling write operations with varying clock phases, thereby eliminating dedicated calibration circuits.
2Reliability
If dedicated circuits like PLL or DLL are used for calibration, then calibration reliability is improved, but productivity decreases due to additional circuit overhead
Solution Approach 1:
The memory device performs self-calibration using its own internal resources without requiring external dedicated calibration circuits. The control circuit generates calibration data by controlling write operations to memory cells, and the device automatically adjusts timing based on this calibration data, achieving reliable calibration while maintaining system efficiency.
Solution Approach 2:
The patent merges the calibration function with normal memory operations. The calibration data is generated and processed using the same memory cell arrays and control logic used for data storage and retrieval, eliminating the need for separate calibration circuits and improving overall system productivity.
3Measurement precision
If calibration operation is performed independently of data read operations, then calibration accuracy is improved, but loss of time increases
Solution Approach 1:
The patent enables continuous operation by performing calibration and data read operations simultaneously without interrupting either. The memory device controls different memory cell arrays to execute calibration operations while other arrays continue normal data read operations, ensuring calibration accuracy is maintained without causing time loss or performance degradation.
Solution Approach 2:
The patent divides the memory system into multiple independent memory cell arrays that can operate simultaneously. One array performs calibration operations while other arrays handle data read operations, allowing parallel execution of calibration and normal operations without mutual interference, thus maintaining both accuracy and time efficiency.
Data Source
AI summary
A semiconductor storage device includes a first chip and a second chip each including a memory cell and configured to receive a same toggle signal. Upon receiving a first command, the first chip executes a first calibration operation to calibrate a duty ratio of an output signal generated in response to the toggle signal while data is read out from the second chip in response to the toggle signal.