Parallel Read Functional Unit for Microprocessor Encryption

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Solution Overview

Problem

Existing microprocessors face inefficiencies in table lookups for symmetric-key ciphers, particularly in scalable designs, leading to increased circuit area and reduced speed due to complex logic circuits and limitations in handling multiple tables and table widths.

Innovation Solution

A parallel read functional unit for microprocessors is introduced, featuring two source registers, two banks of memory tables, a combinational logic circuit, and a decoder circuit, enabling fast parallel data read, write, and manipulation operations. This unit allows for simultaneous access and processing of multiple lookup tables, reducing execution time through optimized instruction sets and hardware design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple lookup tables are used in symmetric-key ciphers, then encryption security and functionality are improved, but circuit area increases and speed decreases due to complex logic circuits

Engineering Contradiction:
Improveencryption securityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the lookup table storage into multiple separate banks (first bank and second bank of memory tables) rather than using a single large table. Each bank can be independently accessed and managed, allowing parallel operations while reducing the complexity of any single memory structure. This segmentation enables the system to handle multiple tables efficiently without proportionally increasing overall circuit complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a bank selection dimension by adding a most significant byte (MSB) of the index to select between different banks. This dimensional approach allows the system to organize lookup tables in a multi-bank structure where tables are distributed across banks, enabling parallel access patterns that reduce critical path delays and improve speed while managing circuit area more effectively.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple lookup tables are used in symmetric-key ciphers, then encryption security and functionality are improved, but execution speed decreases due to complex logic circuits

Engineering Contradiction:
Improveencryption securityVSAvoidexecution speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By segmenting lookup tables into multiple banks, the patent enables parallel access to different tables simultaneously. The first and second banks of memory tables can be accessed in parallel using different index portions, which significantly speeds up encryption operations that require multiple table lookups while maintaining the security requirements of various ciphers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a bank selection dimension using the MSB of the index, which allows the system to route different table access requests to appropriate banks. This dimensional organization enables concurrent access to multiple tables without creating long critical paths, thereby improving execution speed while supporting multiple cipher algorithms.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If complex logic circuits are used to handle multiple tables and table widths, then versatility in supporting different ciphers is improved, but circuit area increases

Engineering Contradiction:
Improvecipher support capabilityVSAvoidcircuit area
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal lookup table access structure that can handle multiple cipher algorithms (DES, 3DES, AES, etc.) and different table widths through a unified multi-bank architecture. The same basic circuit structure supports various ciphers by configuring different banks with appropriate tables, eliminating the need for separate dedicated circuits for each cipher and reducing overall circuit area while maintaining versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter changes to adapt the lookup table system to different ciphers and table widths. By varying the number of banks, the size of each bank, and the indexing scheme (using different portions of the index for different configurations), the system can efficiently support multiple cipher algorithms with different requirements without requiring complex dedicated logic for each case.

Inventive Principle:
Principle #35Parameter changes

4Productivity

If parallel table lookups are implemented, then encryption performance is improved, but hardware resources increase

Engineering Contradiction:
Improveencryption performanceVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the lookup table infrastructure into multiple banks that can be accessed in parallel. This segmentation enables simultaneous table lookups using different portions of the index (with the MSB selecting the bank), achieving parallel encryption performance improvement while keeping each individual bank's hardware requirements manageable and avoiding the need for a single overly complex monolithic structure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8943297B2Parallel read functional unit for microprocessors
Publication Date: 2015.01.27 CORESECURE TECH LLC
  • US8943297B2 patent drawing
  • US8943297B2 patent drawing
  • US8943297B2 patent drawing

AI summary

A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.