Parallel Read-Modify-Write Memory Circuit for High-Speed ECC
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Solution Overview
Problem
Existing memory devices face challenges in performing high-speed read-modify-write operations due to the sequential nature of error correction processes, which are unsuitable for high-speed timing requirements.
Innovation Solution
An error correction circuit and memory device that perform a parallel read-modify-write operation using a first ECC circuit to correct errors and generate merged data, and a second ECC circuit to set partial data to binary values and generate internal parity, allowing simultaneous combination and parity generation of new and previous data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential error correction process is used, then error correction accuracy is maintained, but operation speed deteriorates and cannot satisfy high-speed timing requirements
Solution Approach 1:
The error correction circuit is divided into two independent ECC circuits (first ECC circuit and second ECC circuit) that operate in parallel. The first ECC circuit corrects errors in the second partial data, while the second ECC circuit generates parity for the merged data. This segmentation allows simultaneous execution of error correction and parity generation, resolving the contradiction between maintaining correction accuracy and improving operation speed.
Solution Approach 2:
The patent merges the error correction process with the parity generation process by having both ECC circuits operate simultaneously on different data portions. The first ECC circuit processes the second partial data while the second ECC circuit processes the merged data, and both operations are combined to produce the final corrected data and parity bits in a single parallel operation, eliminating sequential delays.
2Productivity
If parallel processing is implemented, then operation speed is improved, but device complexity increases
Solution Approach 1:
The parallel processing architecture is achieved by segmenting the error correction functionality into two separate but simplified ECC circuits. Each circuit handles a specific portion of the work (error correction vs. parity generation), which reduces the complexity of each individual circuit while enabling parallel operation. This segmentation resolves the contradiction by distributing complexity across multiple simpler components rather than requiring one complex sequential processor.
3Reliability
If masked write operation is performed, then data integrity is improved by retaining old data in some portions, but operation time increases due to sequential read-modify-write process
Solution Approach 1:
The first ECC circuit performs preliminary error correction on the second partial data (old data to be retained) before the merged data is written. By correcting errors in the retained portions in advance, the system ensures data integrity for the masked portions without requiring additional sequential verification steps after the write operation, thus reducing total operation time while maintaining reliability.
Solution Approach 2:
The patent combines the correction of old data (second partial data) and the generation of parity for new merged data into a single parallel operation. This merging of operations ensures that both data integrity (through correction) and operation speed (through parallelism) are achieved simultaneously, resolving the contradiction between reliability and operation time for masked write operations.
Data Source
AI summary
A memory device is configured to perform a parallel read-modify-write operation, which generates a syndrome for first partial data read from a memory cell array and second partial data according to a data mask option, corrects an error of the second partial data, generates merged data by combining second data with the corrected second partial data, and generates an internal parity for the merged data. The memory device sets the second partial data to binary values of 0, generates third data by combining the second partial data set to the binary values of 0 with the second data, generates a third parity for the third data, and generates an internal parity for the merged data based on the syndrome, a partial parity, and the third parity.