Parallel Read-Write Memory Array Reduces ECC Overhead
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Solution Overview
Problem
High-capacity semiconductor memory devices face reliability issues due to reduced capacitance and increased susceptibility to random one-bit errors from cosmic radiation, leading to higher memory overhead for error correction codes (ECC), which is not feasible in large capacity memories.
Innovation Solution
Implementing a memory array parallel read-write method that generates ECC check bits for blocks of data rather than individual data words, reducing the memory overhead required for ECC storage by combining data words into larger blocks and generating fewer ECC check bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC check bits are added to each data word to improve reliability, then error correction capability is improved, but memory overhead increases significantly
Solution Approach 1:
The patent merges multiple data words into a larger data block and generates a single set of ECC check bits for the entire block. This combining approach reduces the total number of check bits required compared to generating separate check bits for each individual data word, thereby reducing memory overhead while maintaining error correction capability.
Solution Approach 2:
The patent changes the parameter of ECC implementation from per-data-word basis to per-data-block basis. By modifying the granularity at which ECC check bits are generated (from individual words to aggregated blocks), the system achieves reduced overhead while preserving reliability through block-level error correction.
2Quantity of substance
If memory capacity is increased by scaling down transistors, then storage capacity is improved, but reliability deteriorates due to reduced capacitance and radiation susceptibility
Solution Approach 1:
The patent combines multiple data words into larger blocks for ECC processing. This merging strategy reduces the overhead proportion, allowing ECC to be applied effectively in high-capacity memories where per-word ECC would be prohibitively expensive in terms of overhead.
Solution Approach 2:
The patent changes the ECC application parameter from fine-grained (per data word) to coarse-grained (per data block). This parameter change makes ECC feasible for large-capacity memories by reducing the relative overhead while maintaining the ability to correct radiation-induced errors.
3Reliability
If more check bits are added to correct multiple errors, then error correction capability is improved, but memory space availability deteriorates
Solution Approach 1:
The patent merges multiple data words into a single data block and generates one set of check bits for the entire block. This approach provides multiple error correction capability for the block while using fewer total check bits than would be required if separate check bits were generated for each individual data word, thus preserving memory space availability.
Data Source
AI summary
A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.