Parallel Reduction Multiplier for RSA Throughput

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data compression and encryption techniques, such as RSA and Montgomery multiplication, face throughput limitations due to serial dependency in modular exponentiation processes, particularly when handling large data sets in rapidly growing data centers.

Innovation Solution

Implementing a parallel reduction multiplier (PRM) MM process that precomputes the reduction coefficient, allowing concurrent partial product accumulation and modulus reduction, breaking the serial dependency and enabling higher throughput by using a look-ahead scaling coefficient computation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional Montgomery multiplication is used to accelerate modular exponential steps of RSA, then computation speed is improved, but serial dependency limits throughput

Engineering Contradiction:
Improvecomputation speedVSAvoidthroughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent segments the Montgomery multiplication process into independent parallel components: precomputation of reduction coefficients, concurrent partial product accumulation, and parallel modulus reduction operations. This segmentation breaks the serial dependency chain while maintaining computational correctness, enabling multiple operations to proceed simultaneously and thereby increasing throughput without sacrificing computation speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by precomputing reduction coefficients before the main multiplication process. This precomputation enables subsequent parallel operations to proceed without waiting for coefficient calculation, eliminating a serial bottleneck and allowing the multiplication and reduction phases to overlap in time, thus improving overall throughput.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data compression and encryption are applied to secure data, then security is improved, but data center performance deteriorates

Engineering Contradiction:
ImprovesecurityVSAvoiddata center performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the operational parameters of the encryption process by implementing parallel reduction multiplication that operates on multiple data elements simultaneously. This parameter change in the computational approach maintains the cryptographic security properties while increasing processing throughput, thereby improving data center performance without compromising security.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If serial dependency in modular exponentiation is maintained, then implementation simplicity is preserved, but throughput is limited

Engineering Contradiction:
Improveimplementation simplicityVSAvoidthroughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the modular exponentiation process into independent parallel stages with well-defined interfaces. Each stage (precomputation, multiplication, reduction) can be implemented as a separate module, maintaining implementation simplicity through modular design while enabling parallel execution to increase throughput.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10498532B2Parallel computation techniques for accelerated cryptographic capabilities
Publication Date: 2019.12.03 INTEL CORP
  • US10498532B2 patent drawing
  • US10498532B2 patent drawing
  • US10498532B2 patent drawing

AI summary

Computing devices and techniques for performing modular exponentiation for a data encryption process are described. In one embodiment, for example, an apparatus may include at least one memory logic for an encryption unit to perform encryption according to RSA encryption using a parallel reduction multiplier (PRM) MM process, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one wireless transmitter, the logic to precompute a reduction coefficient, determine an operand product and a reduction product in parallel, the reduction product based on the reduction coefficient, and generate a MM result for the PRM MM process based on the operand product and the reduction product. Other embodiments are described and claimed.