Parallel Regex Circuit for High-Throughput Data Processing

The patent replaces the mechanical system of a general-purpose CPU executing software instructions with a dedicated hardware regular expression processing circuit. This circuit uses specialized logic elements, state machines, and parallel processing architectures to evaluate regular expressions directly in hardware, eliminating the overhead of instruction fetching, decoding, and sequential execution that limits CPU performance. The hardware implementation provides deterministic, high-speed matching capable of achieving multi-gigabit throughput.

The patent segments the regular expression processing function from the general-purpose CPU and implements it as a separate, dedicated hardware circuit. This segmentation allows the regex processing to occur in parallel with other CPU tasks, removes contention for CPU resources, and enables the regex engine to operate at line rate without being bottlenecked by CPU clock cycles and instruction pipeline limitations.

The patent designs a universal regular expression processing circuit that can be configured to evaluate different regular expressions through programmable parameters and lookup tables. This single versatile circuit can handle multiple regex patterns by loading different configuration data, eliminating the need for dedicated hardware for each regex pattern and reducing overall system complexity while maintaining high throughput capability.

The patent transitions from sequential single-threaded regex evaluation to parallel multi-threaded evaluation within a unified hardware architecture. By organizing the processing circuit to handle multiple input streams and regex patterns simultaneously through spatial parallelism, the system achieves high throughput without proportionally increasing device complexity, as the parallelism is integrated into a cohesive control structure.