Parallel Rejection Sampling Circuit for Lattice Key Throughput
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Solution Overview
Problem
The advent of quantum computers poses a significant threat to the security of existing public-key cryptosystems, as they can potentially be broken by Shor's algorithm, necessitating the development of quantum-resistant algorithms like lattice-based cryptosystems.
Innovation Solution
A cryptographic rejection sampling unit with parallel rejection bounded sampling circuits and a controller to generate and write valid coefficients to memory, ensuring secure key generation resistant to quantum attacks, using a lattice-based system with a RejBounded unit to sample polynomial coefficients from a bounded distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If quantum computers are used to break cryptosystems, then existing public-key cryptosystems can be broken, but lattice-based cryptosystems remain secure
Solution Approach 1:
The patent converts the threat of quantum computing into a benefit by implementing lattice-based cryptography, which is specifically designed to be secure against quantum attacks. The RejBounded sampling unit generates cryptographic keys using lattice-based mathematical structures that remain computationally infeasible to break even with quantum algorithms like Shor's algorithm.
2Reliability
If rejection sampling is used to generate polynomial coefficients, then secure keys can be generated, but computational time is consumed
Solution Approach 1:
The patent segments the rejection sampling process into multiple parallel rejection bounded sampling circuits that operate simultaneously. Each circuit processes independent samples from the random bit string, and the results are collected in a FIFO queue. This parallelization maintains the security requirements of rejection sampling while significantly reducing the total computational time needed to generate sufficient polynomial coefficients.
Solution Approach 2:
The patent performs preliminary actions by pre-generating random bit strings and pre-processing samples through the parallel rejection sampling circuits before the actual key generation is needed. The FIFO queue stores valid coefficients in advance, allowing the key generation process to access pre-computed values and reduce waiting time.
3Productivity
If parallel rejection bounded sampling circuits are used, then throughput is improved, but hardware complexity increases
Solution Approach 1:
The patent divides the sampling function into multiple identical parallel rejection bounded sampling circuits, each handling independent samples. This segmentation enables throughput improvement while keeping each individual circuit simple and modular, making the overall hardware design manageable despite the increased number of components.
Solution Approach 2:
The patent creates a universal sampling framework where the same rejection bounded sampling circuit can process different random bit strings and generate valid coefficients for various cryptographic operations. The FIFO queue and multiplexer provide universal interfaces that work with different numbers of parallel circuits, making the hardware design flexible and adaptable.
Data Source
AI summary
A cryptographic rejection sampling unit includes n parallel rejection bounded sampling circuits coupled to receive n, four-bit samples in a cycle from a buffer containing a random bit string, where n is an integer having a value of at least 8. A first in-first out queue is coupled to receive valid output from the rejection bounded circuits. A multiplexer is coupled to the queue and configured to provide four valid coefficients in the cycle. A controller is coupled to control valid output provided from the queue to the multiplexer, to track a number of valid outputs in the queue, and to control the multiplexer to output the four valid coefficients. A method uses the cryptographic rejection sampling unit to generate and write the valid coefficients to a memory.