Parallel Set and Reset Programming for ReRAM Arrays
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Solution Overview
Problem
Current ReRAM programming methods are serial, leading to inefficiencies due to the need for separate set and reset operations, creation of masks, and verification processes, which increase programming time.
Innovation Solution
Implementing a parallel reset and set programming method for ReRAM arrays using controllers and multiplexers to enable simultaneous programming of ReRAM cells within a word line, with control signals determining whether to apply high or low voltages to bit and source lines for each cell, allowing for parallel execution of set and reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serial set and reset operations are performed separately, then programming correctness is ensured, but programming time increases
Solution Approach 1:
The patent segments the programming operation into independent set and reset operations that can be executed in parallel. Each bit's set/reset status is determined independently through comparison logic, and corresponding voltage signals are generated independently for each bit position, allowing simultaneous execution without interference.
Solution Approach 2:
The patent performs preliminary comparison between new data and old data to generate control signals for each bit position before the actual programming operation. This preliminary action determines which bits need set operations, which need reset operations, and which remain unchanged, enabling parallel execution of all necessary programming operations in a single step.
2Productivity
If parallel set and reset operations are implemented, then programming speed increases, but control circuit complexity increases
Solution Approach 1:
The patent employs universal control logic that generates both set and reset control signals through a single comparison mechanism. The same comparison circuitry that identifies bits needing programming also determines whether each bit requires a set or reset operation, eliminating the need for separate control paths and reducing overall circuit complexity despite enabling parallel operations.
Solution Approach 2:
The patent introduces control signal generation circuitry as an intermediary between data comparison and voltage application. This intermediary layer translates comparison results into appropriate control signals for each bit position, managing the complexity of parallel control through systematic signal generation rather than direct complex switching logic.
3Measurement precision
If separate set and reset verification steps are performed, then data accuracy is ensured, but processing overhead increases
Solution Approach 1:
The patent merges the verification process into a single unified operation performed after parallel set and reset execution. Instead of separate verification steps for set and reset operations, a single comparison between the programmed data and expected new data verifies all bits simultaneously, reducing processing overhead while maintaining complete data accuracy verification.
Data Source
AI summary
A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.