Parallel Resistor Circuit for On-Die Termination Impedance Matching
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Solution Overview
Problem
Conventional parallel resistor circuits in on-die termination (ODT) devices face significant resistance variations due to process variations, leading to errors in impedance matching and accurate calibration, which complicates high-speed data transmission and output data distortion.
Innovation Solution
A parallel resistor circuit with multiple units having different resistivities, where at least one unit comprises resistors connected in parallel, allowing for precise control of resistance through calibration codes to minimize variations and maintain accurate impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional parallel resistor circuits are used in ODT devices, then the device can perform basic termination function, but resistance variations occur due to process variations leading to impedance matching errors
Solution Approach 1:
The patent changes the parameter of resistance by using multiple resistor units with different resistivity values (first, second, and third resistivities) instead of a single resistor. This allows the circuit to compensate for process variations by selecting and combining resistors with appropriate resistivities to achieve the target termination resistance, thereby improving impedance matching accuracy while maintaining resistance value consistency despite manufacturing variations
Solution Approach 2:
The patent employs a composite approach by combining multiple resistor units with different resistivity characteristics into a single parallel resistor circuit. This composite structure allows the circuit to leverage the advantages of different resistor materials and processes, achieving more stable and accurate termination resistance by compensating for individual resistor variations through the parallel combination of diverse resistor units
2Manufacturing precision
If multiple parallel resistor units with different resistivities are used, then resistance variation is reduced, but device complexity increases
Solution Approach 1:
The patent segments the termination resistance function into multiple independent resistor units with different resistivities. Each resistor unit can be independently controlled by separate control signals, allowing the circuit to achieve precise resistance control by selectively activating specific resistor units. This segmentation approach manages complexity by breaking down the resistance control function into manageable, independently controllable modules
Solution Approach 2:
The patent implements dynamic control of the parallel resistor circuit by using control signals to selectively activate or deactivate specific resistor units based on calibration results and operating conditions. This dynamic configuration allows the circuit to adapt its resistance value in real-time, optimizing performance while managing complexity through software-controlled selection rather than fixed hardware configuration
3Reliability
If calibration is performed to compensate for process variations, then impedance matching accuracy improves, but calibration time and complexity increase
Solution Approach 1:
The patent performs calibration in advance during the initialization phase, storing the calibration results (optimal resistor unit combinations) for later use. By pre-determining the best configuration for different process conditions, the system avoids time-consuming real-time calibration during operation, thus improving impedance matching accuracy while minimizing calibration time loss during actual data transmission
Solution Approach 2:
The calibration circuit automatically determines the optimal resistor unit configuration based on measured conditions and stores this information for self-adjustment during operation. The system uses the calibration results to automatically select the appropriate resistor units without requiring manual intervention or continuous calibration, thereby improving accuracy while reducing the time and complexity of the calibration process
Data Source
AI summary
A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up or pull down a predetermined node and compare a voltage of the predetermined node with a reference voltage to generate calibration codes, by using parallel resistor units that are turned on or off in response to the calibration codes. An output driver is configured to terminate a data output node to a pull-up or pull-down level to output data, by using the parallel resistor units. At least one of the parallel resistor units having at least two resistivities includes resistors with different resistivities connected to each other in parallel.