Parallel-Resistor DAC Switching for Faster Settling
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Solution Overview
Problem
Digital-to-analog converters (DACs) face limitations in conversion speed due to settling time, which is influenced by output resistance and capacitive load, and reducing this speed can compromise resistor matching and increase power consumption.
Innovation Solution
A parallel resistors architecture (PRA-DAC) that temporarily reduces output resistance during coarse settling, using switch networks to adjust resistive elements, allowing for increased conversion speed without affecting linearity or increasing power consumption during fine settling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the output resistance Rout is reduced to decrease settling time, then conversion speed is improved, but power consumption increases during fine settling
Solution Approach 1:
The patent applies dynamics by making the output resistance variable rather than fixed. The switch network dynamically reconfigures the resistive elements between coarse settling and fine settling phases, temporarily reducing output resistance during coarse settling to speed up conversion, then restoring it during fine settling to reduce power consumption and maintain precision.
Solution Approach 2:
The patent uses periodic action by dividing the conversion process into distinct phases (coarse settling and fine settling) with different resistance configurations. The switch network periodically transitions between these states based on the conversion stage, allowing high speed during coarse settling and low power consumption during fine settling.
2Speed
If the output resistance Rout is reduced to decrease settling time, then conversion speed is improved, but resistor matching is affected, degrading linearity
Solution Approach 1:
The patent makes the resistance configuration dynamic, using switch networks to temporarily alter the resistive element connections only during coarse settling when high speed is needed. During fine settling, the original resistor matching is restored, ensuring linearity is maintained when precision is most critical.
Solution Approach 2:
The conversion process is segmented into coarse settling and fine settling phases, each with optimized resistance configurations. The switch network segments the resistive elements into different operational groups, allowing independent optimization of speed and precision for each phase without compromising the other.
3Productivity
If the settling time is decreased to increase conversion speed, then productivity is improved, but the output impedance becomes variable, affecting performance
Solution Approach 1:
The patent accepts temporary variability in output impedance during coarse settling to achieve high conversion speed, then restores stable output impedance during fine settling. The switch network dynamically adjusts the resistive configuration to prioritize speed when needed and stability when precision is required.
Solution Approach 2:
The output impedance is periodically adjusted between two states: a lower impedance state during coarse settling for fast conversion, and a stable nominal state during fine settling for accurate settling. This periodic reconfiguration allows the system to achieve high productivity while maintaining performance stability when needed.
Data Source
AI summary
A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed.