Parallel Resistor Prebiasing for Resistive Memory Readout Latency
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Solution Overview
Problem
Existing resistive memory technologies face challenges in efficiently determining the actual cell state of multi-level cell (MLC) resistive memory cells due to slow readout times and susceptibility to noise and drift, particularly when using voltage-based metrics, which are essential for high-density memory applications.
Innovation Solution
A device comprising a sensing circuit, a settling circuit, and a prebiasing circuit with a parallel resistor is used to reduce the effective resistance seen by the prebiasing circuit, allowing for faster readout of voltage-based cell state metrics by minimizing settling time and improving tolerance to drift and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage-based metrics are used to read resistive memory cell states, then measurement precision is improved, but readout time increases due to slow settling
Solution Approach 1:
The patent applies preliminary action by introducing a prebiasing circuit that pre-charges the bitline capacitance before the actual read operation. This prebiasing step brings the bitline voltage close to the expected final voltage level, significantly reducing the settling time required during the actual read operation. The prebiasing circuit stores energy in advance and applies it to accelerate the voltage settling process, thereby resolving the contradiction between measurement precision and readout speed.
2Quantity of substance
If multi-level cell functionality is implemented to increase storage capacity, then cost per bit is reduced, but readout speed decreases due to increased complexity
Solution Approach 1:
For multi-level cell operations, the prebiasing circuit is particularly beneficial as it accelerates the settling process for multiple resistance level distinctions. By pre-charging the bitline to appropriate voltage levels corresponding to different cell states, the circuit enables faster differentiation between multiple resistance levels, thereby maintaining high readout speed despite the increased complexity of MLC functionality.
3Device complexity
If conventional read circuits are used without prebiasing, then device complexity is minimized, but settling time increases leading to slower readout
Solution Approach 1:
The prebiasing circuit implements preliminary action by pre-charging the bitline capacitance before the read operation. This additional circuit element, while increasing device complexity, dramatically reduces settling time by providing advance energy storage and voltage preparation. The benefit of faster readout outweighs the moderate increase in circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces the latency time for reading resistive memory cell states, achieving a total latency of approximately 200 ns, with improved separation of memory levels and better tolerance to drift phenomena, while maintaining accurate detection of cell states.
Implementation Method 1
the resistor is configured to reduce an effective resistance seen by the prebiasing circuit
Implementation Method 2
The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage
Implementation Method 3
cell-state is detected via measurements which exploit the differing resistance characteristics to differentiate between possible cell-states
Data Source
AI summary
A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.