Parallel Resonator ADC Topology for High-Order Noise Shaping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional continuous-time delta sigma (CTDS) analog-to-digital converters (ADCs) face challenges in achieving high-order transfer characteristics with a minimal number of operational amplifiers, leading to increased circuit size and power consumption, while also requiring complex design efforts to set and change transfer characteristics.
Innovation Solution
A resonator configuration with a common node and specific resistive and capacitive element connections allows for independent control of transfer function coefficients, enabling easy setting and dynamic change of transfer characteristics, thereby reducing the need for multiple operational amplifiers and simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the order of quantization noise transfer function is increased to improve resolution performance and SN characteristics, then the transfer characteristics are improved, but the number of operational amplifiers increases causing larger circuit size and higher power consumption
Solution Approach 1:
The patent merges multiple operational amplifiers into a single operational amplifier by combining multiple resonators in a parallel configuration. Each resonator contributes to the overall high-order transfer characteristics, allowing the system to achieve the desired resolution performance without proportionally increasing the number of operational amplifiers, thus reducing circuit size and power consumption.
Solution Approach 2:
The single operational amplifier is designed to perform multiple functions by serving as the common amplifier for all parallel resonators. This multi-functional approach allows one operational amplifier to provide the necessary gain and buffering for multiple resonant circuits, thereby achieving high-order transfer characteristics without requiring separate operational amplifiers for each resonator.
2Measurement precision
If the order of quantization noise transfer function is increased to improve resolution performance and SN characteristics, then the transfer characteristics are improved, but the number of operational amplifiers increases causing higher power consumption
Solution Approach 1:
The patent merges multiple operational amplifiers into a single operational amplifier by combining multiple resonators in a parallel configuration. Each resonator contributes to the overall high-order transfer characteristics, allowing the system to achieve the desired resolution performance without proportionally increasing the number of operational amplifiers, thus reducing circuit size and power consumption.
3Ease of manufacture
If conventional second-order resonator configuration is used, then the circuit structure is simple, but the transfer characteristics cannot be easily changed and require great design efforts
Solution Approach 1:
The patent segments the transfer function design into multiple independent resonators, each with its own set of passive components (resistors and capacitors). This segmentation allows each resonator to be independently designed and adjusted, enabling flexible modification of the overall transfer characteristics without redesigning the entire circuit. The passive components can be easily tuned to achieve desired pole and zero locations.
Solution Approach 2:
The patent introduces dynamic adjustability by allowing the passive components (resistors and capacitors) in each resonator to be independently varied. This enables the transfer characteristics to be dynamically adjusted to suit different application requirements, such as changing the pole frequency or damping ratio, without requiring complex active components or control circuits.
Data Source
AI summary
Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.


