Parallel Retimer Paths for Low-Latency Data Links
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Solution Overview
Problem
Current retimers in high-speed serial expansion bus systems, such as PCI Express, introduce significant latency due to their high-latency operations like bit manipulation and equalization, which can compromise performance in data transmission.
Innovation Solution
A retimer system integrating both a full data path and a bit-level data path, where the bit-level path is used for low-latency data transfer and seamlessly switches to the full data path during equalization procedures to reduce latency and maintain signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retimer is used to extend channel reach and improve data quality, then signal quality and equalization are improved, but data transmission latency increases significantly
Solution Approach 1:
The patent segments the retimer's data path into two separate paths: a full data path for equalization operations and a bit-level data path for low-latency data transmission. This segmentation allows the system to perform equalization functions when needed while maintaining a separate, faster path for normal data transmission, thereby resolving the contradiction between signal quality improvement and latency reduction.
Solution Approach 2:
The patent implements dynamic path selection that switches between the full data path and bit-level data path based on operational mode. During equalization procedures, the full data path is activated; during normal operation, the bit-level data path is used. This dynamic switching enables the system to adapt its behavior to current needs, achieving both high signal quality during equalization and low latency during data transmission.
2Reliability
If full data path processing is used for equalization procedures, then equalization results are achieved, but data transfer speed decreases due to additional processing steps
Solution Approach 1:
The patent divides the data processing functionality into two segmented paths: the full data path containing all processing stages (serial-to-parallel conversion, descrambling, decoding, equalization, encoding, scrambling, parallel-to-serial conversion) and the bit-level data path that bypasses these processing stages. This segmentation enables equalization to be performed when needed while maintaining high-speed data transfer through the simplified bit-level path during normal operation.
Solution Approach 2:
The patent performs equalization procedures in advance during link training or recovery states using the full data path, so that once equalization is complete, the system can switch to the bit-level data path for high-speed data transmission without needing to perform equalization processing during active data transfer. This preliminary action ensures signal quality is optimized before high-speed transmission begins.
3Reliability
If a retimer is inserted in the data link to recover and retransmit data, then signal integrity is improved, but round-trip latency increases to 100 nanoseconds or more
Solution Approach 1:
The patent implements dynamic path selection that adapts the data transmission route based on operational state. During normal L0 active state, the bit-level data path is used for minimal latency. During link training or recovery states requiring equalization, the full data path is activated. This dynamic adaptation allows the system to maintain high data quality through proper equalization while minimizing latency during normal operation by using the direct bit-level path.
Solution Approach 2:
The patent extracts the latency-intensive processing functions (serial-to-parallel conversion, descrambling, decoding, equalization, encoding, scrambling, parallel-to-serial conversion) from the normal data transmission path and places them only in the full data path. The bit-level data path retains only essential functions (signal reception, amplification, and retransmission), thereby removing the source of excessive latency while preserving signal integrity through selective use of the full processing path when needed.
Data Source
AI summary
This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. A first sequence of data packets is transferred via the bit level data path of the retimer. While transferring the first sequence of data packets, the data link detects initiation of an equalization procedure based on an initiation data packet in the first sequence of data packets. In accordance with detection of the initiation of the equalization procedure, the data link selects the full data path of the retimer for data transfer over the data link. During the equalization procedure, a second sequence of data packets immediately follows the first sequence of data packets, and is transferred via the full data path of the retimer.