Parallel RF Switch Stacks With Capacitor Balancing for Fast Settling

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Solution Overview

Problem

Conventional RF switches with large FET stacks suffer from slow settling times and non-uniform RF voltage distribution, leading to low power handling capability and high off-state leakage currents.

Innovation Solution

Implementing RF switches with parallel transistor stacks and capacitor networks to balance RF voltages, allowing for faster switching and reduced leakage currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If large FET stacks are used to achieve higher power handling capability, then power handling capability is improved, but settling time becomes relatively slow

Engineering Contradiction:
Improvepower handling capabilityVSAvoidsettling time
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent divides a single large FET stack into multiple smaller FET stacks connected in parallel. Each smaller stack has reduced gate capacitance and faster switching characteristics, while the parallel configuration maintains the overall power handling capability. This segmentation resolves the contradiction by achieving fast settling time through smaller individual units while preserving high power handling through parallel arrangement.

Inventive Principle:
Principle #1Segmentation

2Power

If large FET stacks are used to achieve higher power handling capability, then power handling capability is improved, but non-uniform RF voltage distribution results in low power handling capability

Engineering Contradiction:
Improvepower handling capabilityVSAvoidRF voltage distribution uniformity
Core Design Contradiction:
PowerVSStability of the object's composition

Solution Approach 1:

The patent segments the power handling function across multiple parallel FET stacks, where each stack handles a portion of the total power. This segmentation, combined with individual balancing capacitors for each stack, enables uniform RF voltage distribution across all stacks while maintaining high overall power handling capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces balancing capacitors as intermediary elements connected to each FET stack. These capacitors actively balance the RF voltage distribution across parallel stacks, preventing non-uniform voltage patterns that would limit power handling capability. The balancing capacitors mediate between the parallel stacks to achieve uniform voltage distribution.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If conventional techniques are used for balancing RF voltage distribution, then RF voltage distribution is balanced, but leakage currents become undesirably high

Engineering Contradiction:
ImproveRF voltage distribution uniformityVSAvoidleakage currents
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by placing individual balancing capacitors at each FET stack location rather than using a conventional centralized balancing technique. This localized approach allows each stack to be independently balanced, achieving uniform RF voltage distribution while minimizing leakage currents through optimized local capacitance values tailored to each stack's characteristics.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12395171B2Switch circuits with parallel transistor stacks and capacitor networks for balancing off-state RF voltages, and methods of their operation
Publication Date: 2025.08.19 NXP USA INC
  • US12395171B2 patent drawing
  • US12395171B2 patent drawing
  • US12395171B2 patent drawing

AI summary

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. A first network of one or more balancing capacitors includes a first capacitor coupled across multiple transistors of the first plurality of transistors. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. A second network of one or more balancing capacitors includes a second capacitor coupled across multiple transistors of the second plurality of transistors.