Parallel ROM Test Architecture With Signature-Based Fault Detection
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Solution Overview
Problem
In embedded systems, serial testing of read-only memories (ROMs) limits memory test time and increases costs, making it unsuitable for applications requiring fast boot-up and periodic testing, especially in automotive systems where reducing testing time is crucial for safety and performance.
Innovation Solution
Implementing parallel testing of ROMs by using a memory enable logic circuit to distribute test signals among ROMs, allowing each to perform read operations at different clock cycles of a higher frequency BIST controller clock, and combining the results to calculate a test signature for fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial testing of ROMs is used, then device complexity is reduced, but testing time increases and productivity decreases
Solution Approach 1:
The patent segments the testing process by dividing multiple ROMs into separate testable units and allocating dedicated test data paths to each ROM. This segmentation allows parallel testing of multiple ROMs simultaneously, increasing testing speed while managing complexity through structured organization of test resources.
Solution Approach 2:
The patent merges multiple ROM test operations into a unified parallel testing framework where multiple ROMs are tested simultaneously using shared test control logic and combined data path resources. This merging approach increases productivity by executing multiple tests in parallel while controlling complexity through resource sharing.
2Loss of time
If serial testing of ROMs is used, then power consumption is reduced, but testing time increases
Solution Approach 1:
The patent implements periodic action by enabling ROMs to be tested in alternating time slots or cycles, allowing parallel testing operations to occur periodically. This approach reduces overall testing time while managing power consumption through controlled activation of test circuits at different time periods, rather than continuous operation.
Solution Approach 2:
The patent applies dynamics by making the test enable signals dynamic and time-varying, allowing different ROMs to be activated for testing at different clock cycles. This dynamic allocation of test resources enables parallel testing to complete faster while spreading power consumption over time, avoiding peak power demands.
3Productivity
If parallel testing of ROMs is implemented, then testing time is reduced, but device complexity increases
Solution Approach 1:
The patent implements universality by designing a multi-functional test controller that can manage multiple ROMs using the same control logic and data path structures. This universal approach increases testing throughput while controlling complexity by reusing the same test resources across multiple ROMs rather than requiring dedicated complex control for each ROM.
Solution Approach 2:
The patent introduces intermediary elements such as test enable signals and multiplexers that mediate between the test controller and multiple ROMs. These intermediaries simplify the control complexity by providing a standardized interface layer, allowing parallel testing of multiple ROMs through coordinated signal management rather than direct complex control of each ROM.
4Speed
If parallel testing of ROMs is implemented, then testing speed increases, but peak power consumption increases
Solution Approach 1:
The patent applies dynamics by making test enable signals time-varying and clock-cycle-dependent, allowing different ROMs to be activated at different times during the testing process. This dynamic approach increases testing speed through parallel operations while spreading power consumption across multiple clock cycles, thereby reducing peak power demands compared to simultaneous activation of all test circuits.
Data Source
AI summary
A device including a controller coupled to memory components via a forward data path, and a signature register coupled to the memory components via a backward data path. The controller provides memory address signals and a controller clock signal to the memory components via the forward data path, which includes first circuitry to provide test-enable signals to the memory components that enable the memory components to read stored memory values. The backward data path includes second circuitry to receive from the memory components a set of memory signals and combine them into a combined signal. Each memory signal is associated with a respective one of the memory components and includes at least one stored memory value read from the corresponding memory component. The signature register calculates a test signature based on the combined signal and compares the test signature to an expected signature.