Parallel ROM Test Architecture for Faster Embedded Memory BIST
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Solution Overview
Problem
Serial testing of ROMs in embedded systems limits memory test time and increases costs, making it unsuitable for applications requiring fast boot-up and periodic testing, especially in automotive systems where safety and efficiency are critical.
Innovation Solution
Implementing parallel testing of ROMs using a BIST controller, memory enable logic circuit, and multiplexer to distribute test signals among ROMs, allowing each to read memory values at different clock cycles, thereby reducing testing time and peak power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial testing of ROMs is used, then device complexity is reduced, but memory test time increases
Solution Approach 1:
The patent segments the testing process by dividing multiple ROMs into parallel test channels. Each ROM is tested simultaneously in its own channel using separate test-enable signals and clock cycles, allowing concurrent execution of tests that would otherwise be performed sequentially. This segmentation directly reduces total test time while maintaining manageable system complexity through modular organization.
Solution Approach 2:
The patent transitions from one-dimensional serial testing to multi-dimensional parallel testing by adding the time dimension through interleaved clock cycles. Different ROMs are activated at different clock cycles (e.g., ROM1 at even cycles, ROM2 at odd cycles), creating a temporal dimension that enables parallel operation without requiring all ROMs to operate simultaneously, thus reducing complexity while accelerating testing.
2Loss of time
If parallel testing of ROMs is implemented, then memory test time is reduced, but device complexity increases
Solution Approach 1:
The patent employs universal test-enable logic and multiplexers that serve multiple ROMs through time-division multiplexing. The same control structures and data paths are reused across different ROM channels by activating them at different clock cycles, reducing the need for dedicated hardware for each ROM and thereby limiting the increase in device complexity while achieving parallel testing.
Solution Approach 2:
The patent implements periodic activation of different ROMs using interleaved clock cycles and phased test-enable signals. ROMs are activated in a periodic sequence (e.g., ROM1 at cycles 0, 2, 4...; ROM2 at cycles 1, 3, 5...), allowing parallel testing throughput while using simple periodic control logic rather than complex arbitrary scheduling, thus balancing speed improvement with complexity management.
3Use of energy by moving object
If parallel testing of ROMs is implemented, then peak power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent uses periodic, non-overlapping activation of different ROMs through phased clock cycles and test-enable signals. By activating ROMs sequentially in different clock cycles rather than simultaneously, the system reduces peak power consumption while maintaining parallel testing throughput. This periodic activation pattern achieves power reduction with relatively simple control logic.
Solution Approach 2:
The patent implements dynamic clock gating and test-enable control that adapts the activation of different ROM channels based on the current clock cycle phase. This dynamic control allows the system to activate only the necessary ROMs at each cycle, reducing unnecessary power consumption while maintaining the ability to test multiple ROMs in parallel through time-division multiplexing.
Data Source
AI summary
An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.