Parallel Route Interconnect Block for SoC Transaction Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Hierarchical circuit-switched interconnects in System-on-Chip (SoC) systems face issues with reduced connectivity and performance due to shared routes and contention, leading to potential blocking of transactions, especially in blocking protocols like AMBA 3 AXI, where transactions cannot be removed until completion.
Innovation Solution
An interconnect block with two parallel connecting routes between portions allows initiators to access recipients via either route, maintaining the selected route for the transaction duration while providing an alternative route for other transactions, reducing the likelihood of slow transactions blocking others and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If hierarchical circuit-switched interconnect structure is used, then area and maximum clocking frequency are improved, but connectivity is reduced and performance is reduced due to shared routes and contention
Solution Approach 1:
The interconnect is divided into hierarchical portions (first portion and second portion) with multiple parallel connecting routes between them. This segmentation allows the interconnect to maintain reduced area through hierarchical structure while providing multiple alternative paths that preserve connectivity and enable load balancing across portions.
2Area of stationary object
If hierarchical circuit-switched interconnect structure is used, then area is improved, but performance is reduced due to route contention blocking transactions
Solution Approach 1:
The interconnect dynamically selects between multiple parallel connecting routes based on current transaction demands and route availability. This dynamic routing capability allows the system to adapt to changing traffic patterns, avoiding route contention and maintaining high transaction throughput while preserving the area benefits of hierarchical structure.
3Area of stationary object
If single shared route is used between portions, then area is reduced, but latency increases due to blocking by slow transactions
Solution Approach 1:
The system changes the routing parameter by providing multiple parallel connecting routes between portions instead of a single shared route. This allows transactions to be routed through alternative paths when one route is blocked by slow transactions, significantly reducing latency while maintaining the area efficiency of the hierarchical structure through selective route usage.
Data Source
AI summary
An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is operable to provide a data route between said initiator device and said recipient device via said at least two parallel connecting routes and to maintain said data route for the duration of said transaction.