Parallel-Row Semiconductor Unit for Low Parasitic Inductance
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Solution Overview
Problem
Existing power semiconductor devices face challenges in reducing parasitic inductance, which leads to surge voltages during switching operations in high-power applications, particularly in two-in-one semiconductor modules where multiple semiconductor units are connected in parallel.
Innovation Solution
The semiconductor unit design features transistor chips arranged in parallel rows with specific conductor layers and a wiring substrate, allowing for parallel current paths between external terminals and main electrodes, reducing mutual inductance between terminals and connectors, thereby minimizing overall parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple semiconductor units are connected in parallel to increase power capacity, then the power handling capability is improved, but the parasitic inductance increases causing surge voltages during switching operations
Solution Approach 1:
The patent transitions from planar busbar arrangements to a three-dimensional stacked configuration where semiconductor units are vertically stacked with intermediate substrates. This vertical stacking allows current paths to be arranged in different spatial layers, enabling parallel connection for increased power capacity while maintaining compact current loops that minimize parasitic inductance through optimized vertical current flow paths.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor units are stacked within a compact vertical space, with each unit containing transistors and diodes integrated on separate substrates. The intermediate substrates nest the different functional layers (transistor layer, diode layer) within each unit, and multiple units are nested vertically to achieve high power capacity in a small footprint while controlling inductance through compact current paths.
2Object-affected harmful factors
If busbars are arranged parallel to reduce parasitic inductance, then the inductance is reduced, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The intermediate substrates serve multiple functions: they provide mechanical support for stacking semiconductor units, establish electrical connections between stacked units, define current flow paths to minimize inductance, and enable thermal management. This multi-functionality reduces the need for separate specialized components, thereby simplifying the overall device structure while achieving low inductance performance.
Solution Approach 2:
The patent merges the functions of multiple semiconductor units, busbars, and connection structures into an integrated stacked assembly. The intermediate substrates combine mechanical support, electrical connection, and current path definition functions. By merging these elements into a unified vertical stack rather than separate planar components, the device complexity is reduced while maintaining low parasitic inductance through optimized current flow paths.
3Area of stationary object
If semiconductor units are stacked vertically to reduce footprint, then the area is reduced, but the parasitic inductance between terminals and connectors increases
Solution Approach 1:
The patent moves from planar to vertical current flow paths by stacking semiconductor units vertically with intermediate substrates. This vertical arrangement reduces the horizontal footprint while the intermediate substrates are designed to provide low-inductance vertical connection paths. The current flows vertically through the stacked units via optimized via structures and contact pads on the intermediate substrates, minimizing the loop area and thus the parasitic inductance despite the vertical stacking configuration.
Data Source
AI summary
A semiconductor unit includes: a plurality of transistor chips arranged in a plurality of parallel rows, each transistor chip respectively having a first main electrode on one surface and a second main electrode on another surface; a first conductor layer electrically connected to the first main electrodes of the transistor chips, both corner portions on one end of the first conductor layer being drawn out in a direction in which the rows of transistor chips run; a second conductor layer arranged between the both corner portions of the first conductor layer; and a wiring substrate that is arranged on a side of the second main electrodes of the plurality of transistor chips and includes a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and to the second conductor layer.