Parallel Reed-Solomon Encoder Circuit for Lower-Latency Throughput
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Solution Overview
Problem
High-speed communication systems face challenges in achieving high throughput and reducing hardware requirements for Reed-Solomon encoding due to the complexity and resource-intensive nature of evaluating the remainder polynomial in finite field polynomial division, leading to increased latency and hardware needs.
Innovation Solution
A parallel encoding circuit design that processes multiple input symbols simultaneously by altering the feedback arithmetic of the recursive finite field division, using fewer hardware resources while maintaining throughput, through optimized matrix multiplication and XOR operations, and implementing a buffer circuit to store intermediate results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard Reed-Solomon encoder is used to evaluate the remainder polynomial through recursive finite field division, then the encoding function is correctly performed, but the hardware requirements and computation time increase significantly
Solution Approach 1:
The encoder is divided into N parallel processing channels, each handling a portion of the K input symbols simultaneously. This segmentation allows the remainder polynomial evaluation to be performed in parallel across multiple paths, reducing the iterative complexity from O(K) to O(K/N) while maintaining the same error correction capability through systematic organization of the encoding process
2Productivity
If multiple instances of standard encoders are implemented to increase throughput, then the data rate increases, but the hardware requirements increase linearly
Solution Approach 1:
Multiple encoding operations are merged into a single unified encoder architecture that processes N input symbols simultaneously through parallel paths. The feedback arithmetic operations are combined and shared across all channels, allowing the system to achieve the throughput of N separate encoders while using significantly less hardware by eliminating redundant components and sharing common resources
3Device complexity
If time-division-multiplexed processing is used to process multiple data channels, then hardware requirements are reduced, but the encoding latency increases
Solution Approach 1:
The encoder transitions from sequential time-division processing to spatial parallel processing by adding N parallel processing paths that operate simultaneously. This dimensional change from time to space allows multiple input symbols to be processed in the same clock cycle through parallel feedback arithmetic operations, maintaining low latency while using efficient hardware resources
4Productivity
If parallel processing is implemented to meet high-speed throughput requirements, then the data rate increases, but the hardware resources increase
Solution Approach 1:
The encoder changes the operational parameters by processing N symbols per clock cycle instead of one symbol at a time. By modifying the parallelism degree and using systematic feedback arithmetic with shared resources, the system achieves high throughput equivalent to N sequential encoders while using a constant amount of hardware resources, effectively changing the time-complexity from O(K) to O(K/N)
Data Source
AI summary
In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.