Parallel RX Packet Processing in High-Speed Network Buffers

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-speed networks create an input/output bottleneck as processors, designed primarily for computing, struggle to keep up with data flow, necessitating a technique to accelerate TCP and other packet processing.

Innovation Solution

A system and method for processing packets received via a network, where data and control packets are processed in parallel, utilizing separate processing paths, look-up tables, caches, and duplicate logic to identify correct socket control blocks, and updating control blocks concurrently with packet processing, with tag information prepended to packets for efficient buffering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional sequential packet processing is used, then processing logic is simple, but processor cannot keep up with high-speed data flow

Engineering Contradiction:
Improvepacket processing speedVSAvoidprocessing path complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides packet processing into separate processing paths: a first processing path for control packets and a second processing path for data packets. This segmentation allows simultaneous processing of different packet types, increasing overall processing speed while managing complexity through structured organization of processing logic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces parallel processing dimensions by implementing multiple processing paths that operate simultaneously. Instead of sequential processing along a single dimension, the system processes control and data packets in parallel along different dimensional paths, thereby increasing processing throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If packets are processed in sequence, then processing logic is straightforward, but throughput is limited by processor speed

Engineering Contradiction:
Improvedata throughputVSAvoidpacket processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary actions by pre-processing packet classification and routing decisions before full packet processing. Control packets are identified and routed to appropriate processing paths in advance, reducing the time required for complete packet handling and increasing overall throughput.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuous useful action by maintaining multiple processing paths that operate simultaneously without idle periods. While one path processes control packets, another path processes data packets, ensuring that the processor continuously utilizes available bandwidth and maintains high throughput.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If separate processing paths are implemented for control and data packets, then processing efficiency increases, but system complexity increases

Engineering Contradiction:
Improvepacket processing efficiencyVSAvoidprocessing path structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements universal processing logic that can handle both control and data packets through a common framework. The processing paths share common resources and logic structures, allowing the system to maintain high processing efficiency while reducing overall complexity through resource sharing and standardized handling procedures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7957379B2System and method for processing RX packets in high speed network applications using an RX FIFO buffer
Publication Date: 2011.06.07 NVIDIA CORP
  • US7957379B2 patent drawing
  • US7957379B2 patent drawing
  • US7957379B2 patent drawing

AI summary

A system and method are provided for processing packets received via a network. In use, data packets and control packets are received via a network. Further, the data packets are processed in parallel with the control packets.