Low-Latency Motion Search Using Parallel SAD Accumulators
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Solution Overview
Problem
Current video compression techniques face challenges in achieving low-latency motion search during the process of determining motion vectors between frames, particularly due to the high computational complexity and latency issues associated with hardware implementation and memory access.
Innovation Solution
The implementation of parallel SAD computations using on-chip SRAM to store macroblock and reference window lines, allowing for simultaneous processing across multiple accumulators, and complexity-based selection of partition types to reduce computation costs and increase throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential SAD computation is used for motion search, then computational complexity is reduced, but processing latency increases
Solution Approach 1:
The motion search process is segmented into multiple independent location checks (e.g., 8x8 block positions). Each location check is further divided into partition type evaluations. This segmentation enables parallel processing of different locations simultaneously, reducing overall latency while maintaining manageable complexity for each individual check.
Solution Approach 2:
The patent introduces a new dimension of parallelism by implementing multiple accumulators that can simultaneously compute SAD values for different locations. This transforms the single-threaded sequential computation into a multi-threaded parallel architecture, where latency reduction is achieved through spatial parallelism rather than increasing computational complexity.
2Measurement precision
If comprehensive partition type search is performed, then motion estimation accuracy is improved, but computation cost increases
Solution Approach 1:
The patent implements preliminary action by evaluating multiple partition types in advance and identifying the best match before performing the full motion search. This preliminary evaluation allows the system to select only the most promising partition types for detailed analysis, reducing the overall computation cost while maintaining high motion estimation accuracy.
Solution Approach 2:
Different regions of the video block are assigned different partition types based on local characteristics. The patent evaluates various partition types (e.g., 16x16, 8x8, 4x4) and applies the most appropriate type to each local region, optimizing the balance between accuracy and computation cost by adapting to local image content rather than using a uniform approach.
3Measurement precision
If multiple locations are checked in motion search, then motion vector accuracy is improved, but latency scales with the number of locations
Solution Approach 1:
The patent merges multiple location checks into a single parallel processing stage by implementing multiple accumulators that simultaneously evaluate different locations. This combining of operations into parallel streams allows the system to check multiple locations without latency scaling, as all locations are processed concurrently rather than sequentially.
Solution Approach 2:
The patent creates copies of the computation pipeline for each location being checked. Each accumulator represents a copied instance of the SAD computation logic, allowing simultaneous evaluation of multiple locations. This copying approach enables the system to maintain high motion vector accuracy by checking all locations while preventing latency scaling through parallel execution.
4Speed
If on-chip SRAM is used for storing macroblock lines, then memory access speed is improved, but on-chip memory resource consumption increases
Solution Approach 1:
The patent extracts only the essential data elements (macroblock lines and reference window lines) needed for SAD computation and stores them in on-chip SRAM. By taking out only the critical data required for parallel processing rather than storing entire frames or redundant information, the system achieves fast memory access speed while minimizing on-chip memory resource consumption.
Solution Approach 2:
The patent performs preliminary action by pre-loading macroblock lines and reference window lines into on-chip SRAM before the parallel SAD computation begins. This pre-positioning of data in fast memory ensures that the subsequent parallel processing operations can proceed at high speed without memory access bottlenecks, while the limited on-chip memory is used efficiently for only the data immediately needed by each accumulator.
Data Source
AI summary
Methods and hardware implementations for determining a motion vector between a first frame and a second frame. A block is obtained from the first frame. A reference window is obtained from the second frame. A set of lines are obtained from the block. The set of lines are delayed using a set of delay elements to produce a set of delayed lines. For each location of a search pattern comprising a plurality of locations arranged in a set of rows, a reference window line is obtained from the reference window, a block line is obtained from the set of delayed lines based on which row of the set of rows the location belongs to, and a similarity score of a plurality of similarity scores is accumulated based on the reference window line and the block line. A target location is identified by comparing the plurality of similarity scores.