Parallel Sample-and-Hold Recording Circuit for Low-Power ADC Sharing
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Solution Overview
Problem
Conventional multi-channel biomedical recording systems face challenges in achieving low power consumption and minimal chip area due to high power consumption by buffers and increased area requirements with existing sampling and hold circuit architectures, which are critical for implantable neural recording devices.
Innovation Solution
The implementation of multiple sample-and-hold (S/H) circuits in parallel within the analog-to-digital converter (ADC) extends the tracking time of the ADC, reducing power consumption by more than 10 times for associated buffers while maintaining minimal chip area increments, and optimizing the power and area trade-off for different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If one ADC is shared by multiple analog front-end recording channels by employing an n-to-1 multiplexer, then chip area is reduced, but the sampling frequency of the ADC needs to be increased to n times, requiring a much higher driving capability buffer and increasing power consumption
Solution Approach 1:
The patent divides the single S/H circuit into multiple parallel S/H circuits (e.g., two S/H circuits for two channels). Each S/H circuit independently samples its corresponding channel signal, eliminating the need for a high-speed multiplexer and allowing the ADC to operate at a lower sampling frequency while maintaining high channel density. This segmentation resolves the contradiction by reducing the buffer's driving burden and power consumption without increasing chip area significantly.
2Use of energy by moving object
If one sample and hold (S/H) circuit is implemented for each analog recording channel, then the tracking time of the ADC is extended and power consumption of the buffer is minimized, but the area of the overall system is significantly increased
Solution Approach 1:
The patent merges multiple S/H circuits into a unified parallel architecture where each S/H circuit is dedicated to a specific channel but they share the same ADC resource. This merging approach allows each channel to have its own S/H circuit for optimal tracking time and low buffer power consumption, while the shared ADC and compact layout minimize the overall chip area increase, resolving the contradiction between power efficiency and area constraints.
3Productivity
If the sampling frequency of the ADC is increased to preserve the sampling frequency for each channel in a multiplexed system, then the tracking and conversion time is shortened, but a much higher driving capability buffer is required, increasing overall system power consumption
Solution Approach 1:
The patent segments the sampling process by providing each channel with its own parallel S/H circuit that operates independently at the required sampling frequency. This eliminates the need to increase the ADC's sampling frequency in multiplexed mode, as each channel is sampled simultaneously by its dedicated S/H circuit. Consequently, the buffer's driving burden is reduced, and power consumption is minimized while maintaining high productivity.
Data Source
AI summary
A recording circuit is provided. The recording circuit includes a multiplexing circuit configured to receive a plurality of input signals and to produce a multiplexed output signal including the plurality of input signals, and a plurality of sampling circuits electrically coupled in parallel to each other, each sampling circuit being configured to sample a portion of the multiplexed output signal corresponding to an input signal of the plurality of input signals and the sampling circuits configured to alternately produce an output signal corresponding to the sampled portion.