Parallel SAR ADC Architecture for Faster Conversion
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Solution Overview
Problem
Conventional successive approximation register (SAR) analog-to-digital converters (ADCs) are limited by sequential operation, leading to slow conversion times due to sequential comparison and feedback stages, which results in high energy consumption and complex logic.
Innovation Solution
Implementing two digital-to-analog converters (DACs) in parallel, allowing concurrent comparison and feedback stages, reducing the conversion time by approximately half without increasing switching energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If sequential comparison and feedback stages are used in SAR ADC, then energy consumption is reduced, but conversion speed deteriorates
Solution Approach 1:
The ADC conversion process is segmented into two independent parallel paths: one path handles comparison operations while the other handles feedback operations. This segmentation allows both operations to occur simultaneously rather than sequentially, doubling the conversion speed while maintaining the energy efficiency of the SAR ADC architecture.
Solution Approach 2:
The invention transitions from a single-dimensional sequential operation to a two-dimensional parallel operation by introducing dual DAC arrays and dual comparator paths. This dimensional change enables simultaneous execution of comparison and feedback stages, resolving the speed-energy tradeoff.
2Speed
If dual DAC arrays with alternating switching are used, then conversion speed is improved, but switching energy and logic complexity increase
Solution Approach 1:
The system is divided into two symmetric paths, each with its own DAC array and comparator. This segmentation creates identical operational templates that can be controlled by simple, repetitive logic rather than complex switching networks, reducing overall logic complexity while maintaining high speed.
Data Source
AI summary
A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.