Parallel SAR ADC Digital Path for Lower Conversion Delay
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Solution Overview
Problem
Traditional successive approximation (SAR) analog-to-digital converters (ADCs) face significant delays in the digital path due to the switched capacitor DAC, comparator, and thermometric encoder, which limit data throughput, especially in multiple bit conversions.
Innovation Solution
The implementation of a parallel digital processing path in SAR ADCs, which bypasses the delays introduced by the SAR register and thermometric encoders by using a regenerative latch and multiplexers to directly route the comparator output to the switched capacitor DAC, reducing the overall digital data path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional SAR ADC uses a switched capacitor DAC, comparator, and thermometric encoder in sequence, then the conversion accuracy is maintained, but the digital path delay increases significantly
Solution Approach 1:
The patent segments the digital path into parallel segments: one path processes MSBs through the thermometric encoder while another path processes LSBs separately. This segmentation allows simultaneous processing of different bit groups, reducing the sequential delay while maintaining conversion accuracy through coordinated reconstruction of the full digital output.
Solution Approach 2:
The patent introduces a temporal dimension by overlapping the operation cycles of different bit processing stages. While MSB processing is occurring in one clock cycle, LSB processing is initiated in the next cycle, creating a pipelined architecture that effectively adds a time dimension to the processing flow, thereby reducing overall conversion time without sacrificing precision.
2Measurement precision
If the SAR ADC processes multiple bits sequentially through the SAR register and thermometric encoder, then accurate conversion is achieved, but the data throughput rate is limited
Solution Approach 1:
The patent performs preliminary processing of MSBs in advance during earlier clock cycles, preparing their encoded values before LSB processing completes. This preliminary action allows the system to reconstruct the final digital output more quickly once all bit processing is complete, thereby increasing data throughput while maintaining accuracy through the coordinated combination of pre-processed MSBs and newly processed LSBs.
3Measurement precision
If non-overlapping switch drivers are used for each bit conversion, then control precision is improved, but the overall conversion time increases
Solution Approach 1:
The patent employs periodic clocked control signals that periodically enable different bit processing stages in an overlapping manner. Instead of using non-overlapping control for each bit, the system uses periodic clock cycles to systematically activate MSB and LSB processing stages at different phases, maintaining control precision through synchronized periodic operation while reducing total conversion time through the overlapping periodic cycles.
Data Source
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AI summary
The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.