Parallel SAR ADC Architecture to Eliminate DAC Feedback Delays

Solution Overview

Problem

Conventional successive approximation register (SAR) analog-to-digital converters (ADCs) are limited by sequential operation, leading to high conversion times due to sequential comparison and digital-to-analog converter (DAC) feedback steps, which result in significant delays and energy consumption.

Innovation Solution

Implementing two parallel DAC paths that allow concurrent comparison and feedback stages, reducing the conversion time by approximately half without increasing switching energy, and using a single comparator to compare odd and even bits simultaneously.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If sequential comparison and DAC feedback operations are performed in a conventional SAR ADC, then the conversion process is completed with N comparisons and (N-1) DAC feedback steps, but the total conversion time is significantly increased due to sequential operation

Engineering Contradiction:

Improveconversion accuracyVSAvoidconversion time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The conversion process is segmented into two independent parallel paths: one path handles comparison operations for odd bits while the other path handles DAC feedback operations for even bits. This segmentation allows simultaneous execution of comparison and feedback operations that were previously sequential, effectively halving the conversion time while maintaining N-bit resolution accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements continuous useful action by overlapping the comparison phase of one path with the feedback phase of another path. While the first comparator is comparing odd bits, the first DAC is simultaneously providing feedback for even bits. This continuous overlapping eliminates idle time between operations and maintains productive action throughout the conversion process.

Inventive Principle:

Principle #20Continuity of useful action

2Speed

If two DACs are used to enable overlapping of settling, comparator reset, and regeneration as described in He et al., then conversion speed is improved, but switching energy and logic complexity are significantly increased

Engineering Contradiction:

Improveconversion speedVSAvoidswitching energy

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The conversion process is segmented into two independent parallel paths: one path handles comparison operations for odd bits while the other path handles DAC feedback operations for even bits. This segmentation allows simultaneous execution of comparison and feedback operations that were previously sequential, effectively halving the conversion time while maintaining N-bit resolution accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses a single DAC for both paths rather than two separate DACs. The same DAC is time-multiplexed to serve both the odd-bit comparison path and the even-bit feedback path, reducing the total switching energy required while maintaining the parallel operation benefits.

Inventive Principle:

Principle #33Homogeneity

3Speed

If two DACs are used to enable overlapping operations as described in He et al., then conversion speed is improved, but logic complexity for selecting the appropriate DAC increases

Engineering Contradiction:

Improveconversion speedVSAvoidlogic complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The conversion process is segmented into two independent parallel paths: one path handles comparison operations for odd bits while the other path handles DAC feedback operations for even bits. This segmentation allows simultaneous execution of comparison and feedback operations that were previously sequential, effectively halving the conversion time while maintaining N-bit resolution accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The single DAC is designed to be universal and multi-functional, serving both the odd-bit comparison path and the even-bit feedback path. Control logic selectively directs the DAC output to the appropriate path based on the current operation phase, eliminating the need for complex selection logic that would be required if two separate DACs were used.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP3503407B1Improvements in or related to analog-to-digital converters

Publication Date: 2021.04.07 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)

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AI summary

Described herein is a SAR DAC architecture which uses two parallel DACs (200a, 200b) for performing the comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator (210a, 210b). For fast operation, the comparator performs the comparison with reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by the previous comparison. As a result, the same delay can be used for each DAC feedback and comparison step, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.