Parallel SAR ADC Logic Circuit for Lower Propagation Delay
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly successive-approximation-register (SAR) ADCs, face challenges in reducing propagation delays and conversion time due to serial operation in buffering and data storage processes.
Innovation Solution
Implementing a logic circuit with N unit circuits for data storage and N−1 unit circuits for buffering, where only specific units are enabled during a conversion cycle, allowing parallel operation between storage and buffering to minimize delays and optimize power and speed independently on each path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial operation is used for buffering and data storage in SAR ADC, then device complexity is reduced, but propagation delay and conversion time increase
Solution Approach 1:
The SAR ADC logic circuit is segmented into multiple independent unit circuits (first through fourth unit circuits) that operate in parallel. Each unit circuit handles specific buffering or data storage functions, allowing simultaneous execution of multiple operations without serial dependency, thereby reducing propagation delay while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent transitions from a one-dimensional serial operation sequence to a two-dimensional parallel operation structure by introducing multiple unit circuits that execute buffering and data storage operations simultaneously. This dimensional expansion allows independent optimization of each path and eliminates the time loss inherent in sequential processing.
2Speed
If parallel operation is implemented between storage and buffering, then conversion speed increases, but device complexity increases
Solution Approach 1:
The parallel operation structure is achieved through segmentation into four specialized unit circuits, each with a defined function. This modular approach enables speed improvement through parallelism while controlling complexity by assigning specific roles to each segment, avoiding the need for a completely redesigned complex system.
Solution Approach 2:
Each unit circuit is designed with multi-functionality to handle both buffering and data storage operations as needed. The first and second unit circuits can perform buffering functions, while the third and fourth unit circuits handle data storage, allowing the system to achieve parallel operation without requiring entirely separate dedicated circuits for each function, thus managing complexity.
3Productivity
If all unit circuits are enabled simultaneously, then data processing capacity increases, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of unit circuit enablement based on operational requirements. Not all unit circuits are enabled simultaneously; instead, specific circuits are activated only when needed for particular buffering or storage operations. This dynamic enablement strategy maintains high data processing capacity when required while reducing power consumption during operations that don't require full parallel execution.
Solution Approach 2:
Different unit circuits are enabled with different qualities or intensities based on local requirements. The first through fourth unit circuits are selectively enabled depending on whether buffering, storage, or both operations are needed at a given moment. This localized enablement approach optimizes the balance between processing capacity and power usage by activating only the necessary circuits for each specific operational phase.
Data Source
AI summary
Apparatus and associated methods relate to a logic circuit having a number of unit circuits performing buffering and data storage functionalities in parallel. In an illustrative example, a logic circuit may include N unit circuits for data storage and N−1 unit circuits for buffering. During a conversion cycle, only an ith unit circuit of the N unit circuits and an (i−1)th unit circuit of the N−1 unit circuits may be enabled. Output status of the ith unit circuit of the N unit circuits may be monitored to disable the ith unit circuit, and also enable an (i−1)th unit circuit of the N unit circuits and an (i−2)th unit circuit of the N−1 unit circuits. By performing buffering and data storage in parallel, propagation delays in the SAR logic circuit may advantageously be reduced, and thus, conversion time of a successive-approximation-register (SAR) analog-to-digital converter (ADC) may be advantageously reduced.