Parallel SAR ADC Digital Path for Low-Latency MSB Conversion
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Solution Overview
Problem
Traditional successive approximation (SAR) analog-to-digital converters (ADCs) face significant delays in the digital path due to the switched capacitor DAC, comparator, and thermometric encoder, which affect data throughput rates, especially in multiple bit conversions.
Innovation Solution
The implementation of a parallel digital processing path in SAR ADCs, which bypasses the delays introduced by the SAR register and thermometric encoders by using a regenerative latch and multiplexers to directly route the comparator's output back to the switched capacitor DAC, reducing the overall digital data path delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional SAR ADC architecture with sequential digital processing is used, then the circuit structure is simple and reliable, but the digital path delay is substantial (approximately 2.8 nanoseconds) which limits data throughput rate
Solution Approach 1:
The digital processing path is segmented into multiple parallel paths: a fast path for MSB processing that bypasses the SAR register and thermometric encoder, and a standard path for LSB processing. This segmentation allows different bits to be processed simultaneously through different routes, reducing the overall critical path delay from 2.8ns to approximately 0.7ns while maintaining conversion accuracy.
Solution Approach 2:
The most significant bits are processed in advance through a dedicated fast path that directly connects the comparator output to the DAC control logic, bypassing the sequential SAR register and thermometric encoder stages. This preliminary processing of MSBs allows the conversion to proceed faster since MSBs are determined first in the successive approximation process, thereby reducing the total conversion time and increasing data throughput rate.
2Measurement precision
If the comparator output is routed through the SAR register and thermometric encoder, then the conversion accuracy is maintained, but the settling time increases and data throughput rate decreases
Solution Approach 1:
The conversion process is segmented into two accuracy levels: MSBs are converted through the fast path with reduced processing stages, and LSBs are converted through the standard path with full processing stages including the thermometric encoder. This segmentation maintains overall conversion accuracy while reducing the settling time for the most significant bits, which have the greatest impact on the conversion result.
Solution Approach 2:
The full sequential processing chain (SAR register + thermometric encoder) is applied only to the least significant bits where higher precision is less critical, while the most significant bits use a simplified processing path. This partial application of the full processing chain reduces the overall settling time while maintaining sufficient conversion accuracy for the application.
Data Source
AI summary
The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.