Parallel Scan Chain Diagnosis for IC Defect Identification
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Solution Overview
Problem
Current integrated circuit (IC) scan chain diagnosis is inefficient and imprecise, often identifying multiple flip flops as defective instead of a specific one due to insufficient test data and design limitations, and requires computationally intensive simulations for each manufactured IC.
Innovation Solution
A method and system for performing scan chain diagnosis using parallel pattern simulation, where multiple defect locations are simulated in a single iteration, with sliced failing patterns copied and modified according to assumed defect locations, and diagnosis scores are obtained to identify the most likely defective flip flops, allowing for faster and more accurate defect location identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sequential simulation methods are used for scan chain diagnosis, then comprehensive defect analysis can be performed, but the computational load and time required increase significantly
Solution Approach 1:
The patent segments the scan chain into multiple groups and performs diagnosis on each group separately using parallel simulation. By dividing the large-scale simulation problem into smaller manageable segments, the system achieves both comprehensive defect analysis and improved diagnosis speed through parallel processing of segmented data
Solution Approach 2:
The patent performs preliminary actions by pre-processing test data, identifying candidate defect locations, and preparing simulation patterns before executing the main diagnosis routine. This preliminary preparation enables the subsequent parallel simulation to focus only on relevant scenarios, reducing overall computational load while maintaining accuracy
2Measurement precision
If multiple test patterns are used to improve diagnosis accuracy, then more comprehensive defect coverage is achieved, but the computational complexity and simulation time increase
Solution Approach 1:
The patent merges multiple test pattern simulations into a single parallel simulation framework. By combining the processing of multiple patterns within one unified parallel simulation environment, the system achieves comprehensive defect coverage across multiple patterns while reducing overall computational complexity through resource sharing and parallel execution
Solution Approach 2:
The patent uses copying by creating multiple copies of the simulation engine, each handling a different test pattern or defect scenario simultaneously. This allows comprehensive analysis of multiple patterns without sequentially executing complex simulations, as each copy operates independently in parallel, reducing total simulation time and complexity
3Reliability
If exhaustive simulation of all possible defect locations is performed, then complete diagnosis coverage is achieved, but the computational resources and time required become prohibitively large
Solution Approach 1:
The patent applies partial action by performing simulations only on selected candidate defect locations rather than exhaustively simulating all possible locations. The system identifies and focuses computational resources on the most probable defect locations based on initial analysis, achieving sufficient diagnosis coverage without the prohibitive time cost of exhaustive simulation of every possible defect scenario
Data Source
AI summary
The present disclosure relates to a system and method for performing scan chain diagnosis of an electronic design. The method may include identifying, at a computing device, at least one failing scan chain associated with the electronic design. The method may also include selecting a plurality of defect locations associated with the at least one failing scan chain, wherein the plurality of defect locations corresponds to a number of parallel patterns that a simulator is configured to process. The method may further include selecting a sliced failing pattern set and generating a plurality of copies of a pattern associated with the sliced failing pattern set, wherein each of the plurality of copies corresponds to one of the plurality of defect locations. The method may also include simulating the plurality of copies of the pattern in parallel.