Parallel Scan Chain Testing for Multi-Core Chip Yield
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Solution Overview
Problem
Testing very-large-scale-integration (VLSI) systems with multiple CPU cores integrated on a single chip face inefficiencies due to long test scan chains, which increase test times and costs, and make it difficult to isolate faults in individual CPU blocks, as defects in one block can affect the entire chip.
Innovation Solution
Implementing parallel scan chains that test multiple CPU cores independently, using XOR gates to compare expected and actual test data on-chip, allowing for simultaneous testing and fault isolation, and employing separate scan chains for repairable and critical logic to enable chip functionality even with defective blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan chains from multiple CPU blocks are chained together into one long scan chain, then testing can be performed across all blocks, but test time increases excessively and fault isolation becomes difficult
Solution Approach 1:
The patent divides the single long scan chain into multiple independent parallel scan chains, one for each CPU block. Each scan chain can be tested independently, reducing the time required to test all blocks while maintaining comprehensive testing coverage. The segmentation allows simultaneous testing of multiple blocks without the cumulative time penalty of a single long chain.
2Productivity
If scan chains from multiple CPU blocks are chained together into one long scan chain, then testing can be performed across all blocks, but fault isolation to particular CPU blocks becomes difficult
Solution Approach 1:
By segmenting the scan chains into separate independent chains for each CPU block, the patent enables precise fault isolation. When a fault is detected, the independent structure allows immediate identification of which specific block's scan chain failed, eliminating the need to examine entire long chains to locate defects.
3Difficulty of detecting and measuring
If separate scan chains are used for each CPU block, then fault isolation becomes easier, but multiple test outputs are generated requiring many chip pins and complex external testing
Solution Approach 1:
The patent merges multiple independent scan chain outputs into a single unified test output through an OR gate structure. Each scan chain's output is combined logically, allowing all blocks to be tested independently while presenting a single consolidated output to external testers. This reduces pin requirements and simplifies external testing equipment while maintaining the fault isolation benefits of separate chains.
4Device complexity
If a single long scan chain is used, then fewer chip pins are required, but a defect in one block can block the scan chain and cause the entire chip to fail
Solution Approach 1:
The patent segments the scan chains into independent parallel chains for each CPU block, isolating defects to their respective blocks. A defect in one block's scan chain cannot block other blocks' scan chains, allowing the chip to potentially function with remaining operational blocks even when some blocks fail testing.
Solution Approach 2:
The patent implements local quality by allowing different scan chains to have different characteristics and failure modes specific to each CPU block. Each block's scan chain is independently configured and tested, enabling localized defect management without compromising the entire chip's functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces test time, allows for efficient fault detection and isolation of individual CPU blocks, and enables the chip to function with remaining operational cores, even if some blocks are defective, thereby improving testing efficiency and chip usability.
Implementation Method 1
using XOR gates to compare expected and actual test data on-chip
Data Source
AI summary
A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip and replicated to each processor core's scan chain. The expected test data is compared to scan chain outputs at each processor core. Any mismatches set a test-fail bit for that processor core. Each processor core has repairable scan chains and a separate critical scan chain. Failures in the critical scan chain in any processor core cause the whole chip to fail. Processor cores are disabled that have failures in their repairable scan chains, allowing the chip to be repairable by using the remaining processor cores. Critical scan chains include logic that drives to other blocks on the chip, while repairable scan chains have logic embedded deep within a processor core.