Parallel Scheduling for Packet Switches with Low Delay and Fairness
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Solution Overview
Problem
Existing parallel processing scheduling methods for packet and optical switches face challenges in achieving low delay and fairness among virtual output queues (VOQs) while maintaining low implementation complexity, leading to restricted speed and performance due to high implementation complexity and increased scheduling time as switch size grows.
Innovation Solution
A parallel scheduling method and apparatus that employs a two-stage processing approach with an information managing unit generating request information, a first scheduling unit performing initial scheduling, and a second scheduling unit performing subsequent scheduling using k−1 allocators, where the second scheduling unit selects one allocator to update VOQ state information and transmit grant information, ensuring efficient resource utilization and improved network performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing parallel processing scheduling methods are used, then scheduling speed is improved, but delay increases and fairness among VOQs cannot be guaranteed
Solution Approach 1:
The scheduling process is divided into two distinct stages: a request stage where VOQs generate request information, and a grant stage where allocators distribute time slots. This segmentation allows parallel processing to occur without compromising fairness, as each stage can independently optimize for speed while the combined process guarantees both low delay and VOQ fairness through structured information exchange.
2Speed
If existing parallel processing scheduling methods are used, then scheduling speed is improved, but implementation complexity increases
Solution Approach 1:
Request information and grant information serve as intermediaries that coordinate between VOQs and allocators. These information structures simplify the interaction protocol, allowing parallel processing to be implemented with moderate complexity by standardizing the communication interface between scheduling components.
3Quantity of substance
If switch size increases, then capacity is improved, but scheduling time increases
Solution Approach 1:
By dividing scheduling into request and grant stages, the system can process larger switches more efficiently. The request stage collects all VOQ information simultaneously, while the grant stage distributes time slots in parallel, reducing overall scheduling time as switch capacity increases.
4Speed
If time slot size decreases, then switching speed is improved, but scheduling complexity increases
Solution Approach 1:
Request information is generated in advance during the request stage, preparing all necessary scheduling data before the grant stage begins. This preliminary action allows the time slot to be divided into manageable phases, reducing the complexity of scheduling within smaller time slots while maintaining high switching speed.
Data Source
AI summary
A parallel scheduling apparatus includes an information managing unit generating a first request information for scheduling, a first scheduling unit performing first scheduling and then generating first matching information on the basis of the first request information, and a second scheduling unit performing second scheduling on the basis of the first request information and the first matching information. The parallel scheduling has an advantage of improving the scheduling performance and lowering the implementation complexity, ensuring low delay and transmission fairness among VOQs at low input traffic, being applied to all scheduling algorithms that perform existing multi-iterations, and providing efficient scheduling in a packet switch having a long RTT time or having a very short time slot or cell size, such as an optical switch.