Parallel SDF-NTT Accelerator for Homomorphic Polynomial Multiplication
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Solution Overview
Problem
Existing homomorphic encryption technologies face inefficiencies in performing polynomial multiplication operations due to the large size of homomorphic ciphertexts, leading to impractical computational structures for number theoretic transforms.
Innovation Solution
A homomorphic encryption calculating accelerator with parallel processing units and combination units, utilizing single-path delay feedback (SDF) number theoretic transform (NTT) hardware structures, allows for parallel polynomial multiplication operations across multiple input data, improving computational efficiency without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If NTT-based hardware operator is used to improve computation speed of homomorphic ciphertexts, then computation speed is improved, but the large size of homomorphic ciphertext makes the computational structure impractical
Solution Approach 1:
The patent divides the polynomial multiplication operation into multiple stages, where each stage processes a portion of the computation. The first parallel processing element performs initial polynomial multiplication on input data, and the second parallel processing element continues the multiplication on intermediate results, breaking down the complex operation into manageable segments that can be handled by individual NTT hardware operators.
Solution Approach 2:
The patent transforms the polynomial multiplication problem into a different computational dimension by applying number theoretic transform. Instead of directly multiplying polynomials in the time domain, the system transforms inputs into the frequency domain using NTT, performs element-wise multiplication, and then transforms back, effectively solving the problem in a different mathematical space where the operations are more efficient.
2Reliability
If polynomial multiplication is performed on large homomorphic ciphertexts, then encryption functionality is maintained, but computation time increases significantly
Solution Approach 1:
The patent performs preliminary transformations and preparations before the main polynomial multiplication operation. The system pre-processes input data through the first parallel processing element to generate intermediate results, and pre-configures the NTT hardware operators with appropriate parameters, so that the actual multiplication operation can proceed more efficiently with reduced computation time.
Solution Approach 2:
The patent implements a continuous processing pipeline where the output of one processing element immediately becomes the input of the next. The first parallel processing element continuously generates intermediate results that are fed into the second parallel processing element, which in turn continuously produces final multiplication results, eliminating idle time and maintaining continuous useful action throughout the computation process.
Data Source
AI summary
Disclosed is a homomorphic encryption calculating accelerator which includes a parallel processing unit performing a polynomial multiplication operation in parallel on a plurality of input data corresponding to a degree N polynomial of a homomorphic ciphertext and a combination unit generating a plurality of output data by performing the polynomial multiplication operation on an output of the parallel processing unit. The parallel processing unit includes a first parallel processing element performing the polynomial multiplication operation on first input data among the plurality of input data and a second parallel processing element performing the polynomial multiplication operation on second input data among the plurality of input data. The first parallel processing element and the second parallel processing element are arranged in parallel, and each of the first parallel processing element and the second parallel processing element has a single-path delay feedback (SDF) number theoretic transform (NTT) hardware structure.