Parallel Security Circuit With Tag Integration for Compact IoT Encryption
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Solution Overview
Problem
The challenge of applying advanced encryption standard (AES) technology in the Internet of Things (IoT) is its large hardware size, necessitating a lightweight security solution for distributed components.
Innovation Solution
A security device with an initial value adjustment circuit, a security circuit comprising multiple unit security circuits, and a tag integration circuit, which adjusts initial values and outputs encrypted/decrypted data and tags in parallel, maintaining secret key and nonce size while enhancing security through distributed processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If AES technology is used for security in IoT, then security strength is improved, but hardware size increases
Solution Approach 1:
The security device is divided into multiple unit security circuits (first, second, third unit security circuits) that process data in parallel. Each unit circuit handles a portion of the encryption/decryption task, allowing the system to achieve AES-level security through distributed computation while reducing the complexity and size of individual hardware components.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by introducing multiple unit security circuits that operate simultaneously. This dimensional shift from single-threaded to multi-threaded architecture enables the system to maintain strong security while reducing hardware footprint through efficient resource utilization.
2Loss of time
If distributed processing is implemented, then computation time is reduced, but device complexity increases
Solution Approach 1:
The security device is divided into multiple unit security circuits (first, second, third unit security circuits) that process data in parallel. Each unit circuit handles a portion of the encryption/decryption task, allowing the system to achieve AES-level security through distributed computation while reducing the complexity and size of individual hardware components.
Solution Approach 2:
Multiple unit security circuits are combined to work together on a single encryption/decryption task. The circuits share common resources such as the initial value adjustment circuit, tag integration circuit, and key management functions, achieving parallel processing benefits while avoiding complete duplication of all hardware components.
3Productivity
If multiple unit security circuits are used, then encryption efficiency is improved, but initial value management complexity increases
Solution Approach 1:
The initial value adjustment circuit pre-computes and adjusts initial values for each unit security circuit before the encryption/decryption process begins. This preliminary action ensures that each unit circuit receives the correct initial value based on its index, enabling parallel processing while centralizing the complexity of initial value management in a dedicated circuit.
Solution Approach 2:
The initial value adjustment circuit acts as an intermediary between the key management system and the multiple unit security circuits. It receives the master initial value and key, then generates and distributes appropriate initial values to each unit circuit, simplifying the overall system architecture by centralizing initial value management logic.
Data Source
AI summary
Disclosed is a security circuit which includes an initial value adjustment circuit configured to adjust an initial value based on an index value and output an adjustment initial value, a security circuit including a plurality of unit security circuits, each of which outputs encrypted data or decrypted data or both encrypted and decrypted data and a first tag from input data based on the adjustment initial value, on a secret key, on a nonce, on the input data, and on associated data associated with the input data, and a tag integration circuit that merges the first tags from the plurality of unit security circuits to output a second tag.


