Accelerated IC Reverse Engineering via Parallel SEM Segmentation
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Solution Overview
Problem
The reverse engineering of integrated circuits is inefficient due to the long time required for imaging, especially with the increasing complexity of structures on a limited space, necessitating a faster and more efficient method for image segmentation in Scanning Electron Microscopy (SEM) images.
Innovation Solution
An image processing algorithm that employs filtering and binarization techniques, including low-pass filters and Gaussian Mixture Models, to extract signatures and segment SEM images, while also utilizing parallel processing to split and re-integrate images, thereby reducing the overall imaging timeframe and improving image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional SEM imaging methods are used for reverse engineering, then image quality and structural detail are maintained, but the imaging time becomes excessively long (e.g., 30 days for a 1.5 mm×1.5 mm IC)
Solution Approach 1:
The patent divides the SEM image into multiple sub-images that are processed in parallel across different threads. This segmentation allows the imaging and processing tasks to be distributed concurrently, reducing the total imaging time while maintaining image quality through reintegration of processed sub-images.
Solution Approach 2:
The patent performs preliminary filtering and binarization operations on the SEM images before segmentation and analysis. These preliminary actions prepare the image data in advance, enabling faster processing and reducing the overall time required for reverse engineering while preserving structural details.
2Productivity
If the SEM image is processed using sequential methods, then processing simplicity is maintained, but the processing speed becomes insufficient for modern IC complexity
Solution Approach 1:
The patent implements parallel processing by dividing the SEM image into sub-images handled by multiple threads. This increases processing speed to handle modern IC complexity while managing system complexity through structured thread management and image division.
Solution Approach 2:
The patent replaces traditional sequential mechanical image processing with parallel computational approaches. By substituting the sequential processing mechanism with parallel thread-based computation, the system achieves higher processing speed without proportionally increasing operational complexity.
3Measurement precision
If filtering and binarization are applied to enhance image quality, then structural details are improved, but processing time increases
Solution Approach 1:
The patent applies filtering and binarization operations to segmented sub-images in parallel rather than processing the entire image sequentially. This segmentation approach maintains structural detail enhancement while reducing total processing time through concurrent operation of multiple threads on different image portions.
Solution Approach 2:
The patent performs filtering and binarization as preliminary actions before segmentation and analysis. By completing these time-consuming operations in advance on prepared sub-images, the system enhances structural detail while minimizing the time impact on subsequent processing steps.
Data Source
AI summary
Various embodiments of the present disclosure provide for accelerated segmentation for reverse engineering of integrated circuits. In one example, an embodiment provides for receiving an SEM image for an integrated circuit, performing filtering and binarization with respect to the SEM image, extracting information associated with filter sizes for the filtering, extracting signatures related to a distribution for background pixels and foreground pixels of the SEM image, extracting respective distance to mean signatures for the background pixels and the foreground pixels, and segmenting the SEM image based at least in part on the filter sizes and the respective distance to mean signatures to generate a segmented image for the integrated circuit.