Parallel Semiconductor Layout With Graded Doping for Uniform Performance
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Solution Overview
Problem
Conventional semiconductor devices experience variations in performance among multiple semiconductor elements due to increased intervals, leading to larger device sizes.
Innovation Solution
The semiconductor device incorporates a conductor pattern with a minimum rectangular region surrounding semiconductor elements, where impurity concentrations vary to balance temperature and resistance differences, reducing performance variations without increasing size by strategically placing elements with higher impurity concentrations closer to the center and lower concentrations at the edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If intervals of semiconductor elements are increased to improve heat dissipation, then heat dissipation performance is improved, but device size increases
Solution Approach 1:
The patent applies local quality by differentiating the epitaxial layer structure between center and end portions of the semiconductor device. Specifically, the center portion (first region) has a first epitaxial layer with higher impurity concentration optimized for heat dissipation, while end portions (second region) have a second epitaxial layer with lower impurity concentration. This allows each region to be optimized for its specific thermal conditions without requiring increased overall device size.
Solution Approach 2:
The patent changes the impurity concentration parameter of the epitaxial layer based on position. The first region has a higher impurity concentration (1×10^16 to 1×10^18 atoms/cm³) compared to the second region (1×10^15 to 1×10^17 atoms/cm³). This parameter variation allows the center portion to handle higher thermal loads while maintaining compact device dimensions.
2Reliability
If intervals of semiconductor elements are increased to reduce performance variations, then performance uniformity is improved, but device size increases
Solution Approach 1:
The patent addresses performance uniformity through local quality by creating position-dependent epitaxial layer structures. The center portion elements experience different thermal conditions compared to end portion elements, so the patent optimizes each region's impurity concentration accordingly. This local optimization ensures all elements operate within their optimal performance ranges despite positional differences, achieving uniformity without increasing size.
Solution Approach 2:
The patent uses parameter changes in impurity concentration to compensate for positional performance variations. By adjusting the impurity concentration based on distance from the center, elements at different positions achieve matched electrical characteristics (such as breakdown voltage and on-resistance), ensuring uniform performance across the device without requiring larger spacing.
3Temperature
If impurity concentration is increased in center portion elements, then heat dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into distinct regions (center first region and end second region) with different epitaxial layer characteristics. This segmentation allows independent optimization of each region's impurity concentration during manufacturing, making the complex structure achievable through standardized regional processing techniques rather than requiring complex overall device redesign.
Data Source
AI summary
A semiconductor device includes an insulating substrate, a conductor pattern formed on the insulating substrate, and a plurality of semiconductor elements provided on the conductor pattern and electrically connected in parallel, wherein the conductor pattern has a minimum rectangular region surrounding the plurality of semiconductor elements in a plan view, each semiconductor element of the plurality of semiconductor elements has an epitaxial layer of a first conductivity type, the plurality of semiconductor elements include a first semiconductor element located nearest to a center of gravity of the rectangular region, and a second semiconductor element located farthest from the center of gravity of the rectangular region, and a first impurity concentration in the epitaxial layer of the first semiconductor element is higher than a second impurity concentration in the epitaxial layer of the second semiconductor element.