Parallel Semiconductor Layer Structure for TFT Charging Speed

Solution Overview

Problem

The development of high pixel per inch (ppi) in thin film transistor liquid crystal displays (TFT-LCDs is hindered by the slow charging speed of thin film transistors (TFTs), primarily due to high electric resistance in traditional metal oxide semiconductor layer structures, where amorphous silicon has a mobility of 0.5 to 1.0 and polysilicon has a mobility of 30 to 300, necessitating a reduction in electric resistance to enhance charging speed.

Innovation Solution

A semiconductor layer structure with an insulating substrate and a semiconductor layer comprising source and drain signal access terminals, and 'n'-shaped first and second semiconductor layer patterns formed in parallel, along with a buffering layer between the semiconductor layer and the substrate, which reduces electric resistance and increases charging speed, while allowing for defect compensation to maintain channel conduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a traditional metal oxide semiconductor layer structure is used, then the manufacturing process is simple, but the electric resistance is high and charging speed is slow

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidcharging speed

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The semiconductor layer is divided into multiple parallel patterns (first and second patterns) with different orientations. This segmentation allows each pattern to contribute to current conduction independently, reducing overall electric resistance while maintaining manufacturing feasibility through sequential formation processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention uses a composite semiconductor layer structure combining amorphous silicon and polysilicon in specific patterns. This composite approach leverages the advantages of both materials to achieve lower electric resistance and improved charging speed compared to traditional single-material structures

Inventive Principle:

Principle #40Composite materials

2Device complexity

If the semiconductor layer is formed with a single pattern, then the device complexity is low, but the electric resistance remains high

Engineering Contradiction:

Improvesemiconductor layer structureVSAvoidelectric resistance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The semiconductor layer is segmented into multiple parallel patterns (first and second patterns) with different orientations. This segmentation allows each pattern to contribute to current conduction independently, reducing overall electric resistance while maintaining manufacturing feasibility through sequential formation processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention introduces a new dimension to the semiconductor layer structure by forming patterns with different orientations (first pattern in first direction, second pattern in second direction). This dimensional approach creates multiple conduction pathways that reduce electric resistance without significantly increasing device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If a parallel dual-pattern semiconductor layer structure is formed, then the electric resistance is reduced and charging speed is increased, but the device complexity increases

Engineering Contradiction:

Improvecharging speedVSAvoidsemiconductor layer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor layer is divided into multiple parallel patterns (first and second patterns) with different orientations. This segmentation allows each pattern to contribute to current conduction independently, reducing overall electric resistance while maintaining manufacturing feasibility through sequential formation processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention introduces a new dimension to the semiconductor layer structure by forming patterns with different orientations (first pattern in first direction, second pattern in second direction). This dimensional approach creates multiple conduction pathways that reduce electric resistance without significantly increasing device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10109648B2Semiconductor layer structure

Publication Date: 2018.10.23 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD

AI summary

The present disclosure a semiconductor layer structure having an insulating substrate and a semiconductor layer formed on the insulating substrate. The semiconductor layer includes a source signal access terminal, a drain signal access terminal, a first semiconductor layer pattern and a second semiconductor layer pattern; the first semiconductor layer pattern and the second semiconductor layer pattern formed between the source signal access terminal and the drain signal access terminal in parallel. The present disclosure also provides a method for fabricating a semiconductor layer structure.