Parallel Power Semiconductor Layout for Oscillation Suppression
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Solution Overview
Problem
Conventional semiconductor devices face challenges in suppressing oscillation phenomena during parallel operation of power semiconductor elements due to inadequate inductance between electrodes, leading to reduced bonding strength and efficiency.
Innovation Solution
The semiconductor device design includes power wiring sections that avoid being located on portions of line segments, increasing element-to-element inductance by creating gaps and using projecting portions to connect electrodes, thereby enhancing the suppression of oscillation phenomena and ensuring appropriate bonding of semiconductor elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power wiring sections are placed directly on line segments connecting semiconductor elements, then electrical connection is improved, but inductance between elements decreases causing oscillation phenomena
Solution Approach 1:
The power wiring sections are segmented to avoid continuous placement on line segments. Instead, they are divided into separate sections with gaps positioned at specific locations (e.g., at mounting portions of semiconductor elements), which increases inductance while maintaining electrical connection functionality.
Solution Approach 2:
The wiring layout applies different configurations in different locations: power wiring sections are placed on line segments in some areas to ensure electrical connection, but intentionally create gaps at mounting portions of semiconductor elements to increase inductance and suppress oscillation phenomena.
2Reliability
If gaps are created in power wiring sections to increase inductance, then oscillation suppression is improved, but electrical connection path is interrupted
Solution Approach 1:
The power wiring sections are segmented with gaps positioned strategically at mounting portions of semiconductor elements. These gaps increase inductance for oscillation suppression while the segmented sections remain electrically connected through alternative paths via the substrate's conductive layers.
Solution Approach 2:
The electrical connection is maintained not only through the surface wiring but also through the third dimension via conductive substrates and vias. The gaps in surface wiring are compensated by vertical connections through the substrate, ensuring electrical continuity while achieving inductance increase.
3Reliability
If projecting portions are used to connect electrodes, then inductance is increased and oscillation is suppressed, but device structure becomes more complex
Solution Approach 1:
The projecting portions serve multiple functions: they act as electrical connection terminals, provide mechanical support for bonding, and strategically position wiring sections to create necessary inductance. This multi-functionality reduces the need for separate components and simplifies the overall device structure despite the apparent complexity.
Solution Approach 2:
The projecting portions are designed with optimized geometries (such as rounded edges or specific cross-sectional shapes) that improve electrical contact, reduce stress concentration, and facilitate bonding processes, thereby managing structural complexity through geometric optimization.
Data Source
AI summary
A semiconductor device includes two first semiconductor elements, a first conductor, and a first power terminal. Each of the two semiconductor elements includes a first electrode, a second electrode, and a third electrode and is controlled to switch between an on-state and an off-state by a first drive signal inputted to the third electrode. The first conductor is electrically interposed between the first electrodes of the two first semiconductor elements. The first power terminal is electrically connected to the first conductor and electrically conducting to the first electrodes of the two first semiconductor elements. The two first semiconductor elements are electrically connected in parallel. The first conductor is disposed to avoid being located on a portion of a first line segment connecting centers of the two first semiconductor elements as viewed in a thickness direction of the first conductor.