Parallel Semiconductor Layout for Resonance-Suppressed Switching
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Solution Overview
Problem
Conventional semiconductor devices with power semiconductor elements face challenges in suppressing resonance phenomena when operating multiple semiconductor elements in parallel, leading to inefficiencies in current handling and switching operations.
Innovation Solution
The semiconductor device incorporates a configuration with ferrite beads as circuit components to increase impedance in specific frequency bands, and strategically arranged signal wiring sections and connecting members to reduce inductance and parasitic inductance, thereby suppressing resonance phenomena during parallel operation of semiconductor elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power semiconductor elements are connected in parallel to increase current-carrying capacity, then the current handling capability is improved, but resonance phenomena occur during switching operations
Solution Approach 1:
Ferrite beads are introduced as intermediary components in the signal wiring sections connecting gate terminals. These ferrite beads act as mediators that suppress resonance phenomena during switching operations while allowing the parallel connection of multiple power semiconductor elements to maintain high current-carrying capacity.
Solution Approach 2:
The impedance characteristics of signal wiring sections are modified by incorporating ferrite beads, which change the electrical parameters (increasing impedance) in specific frequency ranges. This parameter change suppresses resonance without affecting the current-carrying capacity of the parallel-connected power semiconductor elements.
2Device complexity
If conventional wiring configurations are used to connect gate terminals, then the device structure is simple, but resonance phenomena and parasitic inductance affect switching efficiency
Solution Approach 1:
Ferrite beads are inserted as intermediary components in the signal wiring path between control terminals and gate terminals. This intermediary structure suppresses parasitic inductance and resonance phenomena, improving switching efficiency while maintaining relatively simple wiring configuration.
Solution Approach 2:
The signal wiring sections are constructed using composite structures combining conventional conductors with ferrite materials. This composite configuration provides both electrical connectivity and resonance suppression, improving switching efficiency without significantly increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses resonance phenomena, enhancing the semiconductor device's ability to handle current and improve switching efficiency by optimizing the impedance and inductance within the device.
Implementation Method 1
The semiconductor device incorporates a configuration with ferrite beads as circuit components to increase impedance in specific frequency bands
Implementation Method 2
strategically arranged signal wiring sections and connecting members to reduce inductance and parasitic inductance
Data Source
AI summary
A semiconductor device includes: a plurality of first semiconductor elements that each have a first electrode, a second electrode, and a third electrode, a switching operation of each of the first semiconductor elements being controlled according to a first drive signal inputted to the third electrode; a plurality of first connecting members respectively bonded to the second electrodes of the first semiconductor elements; a first detection terminal electrically connected to the second electrodes of the first semiconductor elements; and a first signal wiring section electrically interposed between the first detection terminal and the first connecting members. The first semiconductor elements are aligned in a first direction perpendicular to a thickness direction of each of the first semiconductor elements, and are electrically connected to each other in parallel. The first signal wiring section includes a plurality of first pad portions each located between a different pair of first semiconductor elements adjacent to each other in the first direction as viewed in the thickness direction. Each of the first connecting members is bonded to one of the first pad portions and one of the first semiconductor elements that is adjacent to the first pad portion as viewed in the thickness direction.