Parallel Semiconductor Testing via Segmented Test Boards
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Solution Overview
Problem
Current semiconductor testing methods are inefficient as they test devices sequentially, leading to prolonged testing times and reduced throughput, especially during final tests where multiple devices need to be evaluated for functionality and defects.
Innovation Solution
A method and equipment for simultaneously and continuously testing multiple semiconductor apparatuses using test boards with integrated test circuits and software, where test software is loaded in parallel and self-tests are performed independently across multiple boards, allowing for concurrent testing and reduced overall testing time per unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor apparatuses are tested sequentially using conventional methods, then testing can be performed with simple equipment, but testing time per unit apparatus is prolonged and throughput is reduced
Solution Approach 1:
The testing system is segmented into multiple independent test boards (first test board, second test board, etc.), each capable of simultaneously loading test software and performing self-tests on separate semiconductor apparatuses. This segmentation enables parallel testing operations, increasing throughput while maintaining manageable complexity for each individual test board
Solution Approach 2:
Test software is pre-loaded into test circuits before self-tests begin. The first test board completes software loading while the second test board simultaneously performs self-tests, and vice versa. This preliminary action overlap eliminates idle time and reduces total testing time per apparatus
2Productivity
If multiple test boards are used for simultaneous testing, then throughput is improved, but system complexity increases
Solution Approach 1:
Each test board is equipped with its own test circuits and test software, enabling autonomous self-testing operations. The semiconductor apparatuses perform self-tests using their built-in test circuits, reducing the need for complex external testing equipment and simplifying the overall system architecture while maintaining high throughput
Data Source
AI summary
A method for testing a plurality of semiconductor apparatuses, the method including mounting a plurality of semiconductor apparatuses on a first test board, wherein the plurality of semiconductor apparatuses include test circuits, loading test software into the test circuits, performing, by using the test circuits, self-tests on the plurality of semiconductor apparatuses based on the test software, and removing the plurality of semiconductor apparatuses, which have completed the self-tests, from the first test board. Upon completion of the loading of the test software, the test software is loaded into test circuits of a plurality of semiconductor apparatuses on a second test board, while the self-tests are performed on the plurality of semiconductor apparatuses on the first test board.