Parallel Sequence Detection Circuit for Frame Synchronization
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Solution Overview
Problem
Conventional sequence detection methods for frame synchronization or system synchronization in data transmission are inefficient due to serial data input and low detection rates, as they require bit-by-bit processing and multiple detection circuits for parallel data conversion.
Innovation Solution
A sequence detection method and apparatus that acquires i-path data with parallelism, forms detection data sets, extracts data segments within detection windows, and performs correlation operations to determine target sequences, allowing for parallel transmission and reducing time delay and system overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If serial data input is used for sequence detection, then the detection circuit structure is simple, but the detection efficiency is low
Solution Approach 1:
The patent divides the detection process into multiple parallel detection windows, where each window independently processes data segments. This segmentation allows simultaneous detection of multiple potential synchronization sequences, dramatically improving detection efficiency while keeping each individual detection unit relatively simple
Solution Approach 2:
The patent transitions from serial one-dimensional data processing to parallel multi-dimensional detection by introducing multiple detection windows that operate simultaneously. This dimensional expansion allows the system to process multiple data segments in parallel, resolving the contradiction between simplicity and efficiency
2Speed
If bit-by-bit data input is used, then the detection circuit is simple, but the detection speed is slow
Solution Approach 1:
The patent performs preliminary parallel processing of data segments before final synchronization detection. By pre-organizing data into multiple detection windows and preparing data segments in advance, the system achieves faster detection speed without requiring overly complex real-time processing circuits
Solution Approach 2:
The patent creates multiple copies of detection logic across different detection windows, allowing parallel evaluation of multiple data segments. This copying approach enables fast detection by distributing the detection workload across identical simple units rather than using a single complex sequential processor
3Productivity
If multiple detection circuits are used for parallel data conversion, then the detection efficiency improves, but the hardware complexity increases
Solution Approach 1:
The patent designs detection windows that can universally process different data segments using the same detection logic. Each detection window is multi-functional, capable of handling various synchronization sequence patterns, which reduces overall hardware complexity by avoiding specialized circuits for each detection task while maintaining high parallel detection efficiency
Solution Approach 2:
The patent achieves parallel processing by changing the operational parameters of detection windows (such as window position, data segment selection) rather than increasing the complexity of individual detection circuits. This allows multiple simple circuits to work in parallel with different parameters, improving efficiency without proportionally increasing hardware complexity
Data Source
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AI summary
The disclosure discloses a sequence detection method and apparatus, and a computer storage medium. The method includes: acquiring i-path data with the degree of parallelism i; storing x-th i-path data; receiving (x+1)-th i-path data; forming an x-th detection data set by the x-th i-path data and the (x+1)-th i-path data; extracting s paths of data continuously distributed in the detection data set within each of n detection windows to form n data segments; performing a correlation operation between each data segment and a local sequence; and determining, according to a result of the correlation operation, whether a data segment is a target sequence, wherein x is an integer not less than 1, i is an integer not less than 2, n is less than or equal to i, and s is an integer not less than 1 and equal to a bit number of the target sequence.