Parallel-to-Serial Circuit Clock Synchronism Error Detection
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Solution Overview
Problem
Existing parallel-to-serial converter circuits in programmable logic devices are unable to detect disruptions in the synchronism between slow and fast clock signals, leading to errors in serial data transmission.
Innovation Solution
Incorporating an error detection mechanism with a storage element, comparator, and capture portion to monitor the synchronism between clock rates, generating an error detected signal when a disruption occurs, and using a programmable load generator and counter to maintain the clock ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an error detection mechanism is added to monitor clock synchronism, then reliability is improved, but device complexity increases
Solution Approach 1:
A counter is introduced as an intermediary element that counts clock cycles and compares them against expected values. This counter acts as a mediator between the clock signals and the error detection logic, simplifying the overall circuit design by providing a straightforward counting and comparison mechanism rather than requiring complex synchronization monitoring circuits.
Solution Approach 2:
The patent uses a comparison mechanism that copies the expected clock cycle relationship into a reference value stored in the counter. By copying the ideal synchronism relationship into a programmable counter value, the system can detect deviations without requiring complex real-time analysis of clock phase relationships.
2Reliability
If a programmable load generator with counter and comparator is used to maintain clock ratio, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The system dynamically adjusts the loading of the parallel-to-serial converter based on counted clock cycles. Instead of relying on fixed, precision-critical timing relationships, the load generator dynamically enables or disables data loading based on the counter's comparison result, making the system robust to clock signal variations while maintaining proper synchronization.
Solution Approach 2:
A feedback loop is established where the counter continuously monitors the relationship between fast and slow clock cycles, compares the actual count against the expected value, and feeds this information back to the load generator. This feedback mechanism automatically corrects for clock ratio deviations without requiring high-precision manual calibration or manufacturing tolerances.
Data Source
AI summary
A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion; transferring data from the first portion to a second portion; outputting data at a second rate from the second portion, the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.