Parallel-Serial Conversion Circuit With Half-Cycle Timing Adjustment
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Solution Overview
Problem
Existing parallel-serial conversion circuits face challenges in accurately adjusting the output timing of serial data signals with respect to clock signals in semiconductor memory devices, particularly in synchronous semiconductor memory systems where precise timing is crucial for data transfer.
Innovation Solution
A parallel-serial conversion circuit is designed with an adjustment circuit that generates multiple clock signals with different phases based on a reference clock signal, allowing for precise timing adjustment of parallel data signals by converting them into serial 1-bit output signals, enabling phase control and synchronization with the semiconductor memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single clock signal with fixed frequency is used for parallel-serial conversion, then the circuit structure is simple, but the output timing adjustment precision is insufficient
Solution Approach 1:
The single clock signal is segmented into multiple clock signals with different phases (0°, 90°, 180°, 270°). The conversion circuit uses these phase-divided clock signals to selectively convert parallel data bits into serial output at different timing positions, enabling precise timing adjustment without requiring a completely complex circuit architecture.
Solution Approach 2:
The circuit dynamically selects which phase of the clock signal to use for conversion based on the desired output timing. By controlling the selection circuit with timing adjustment signals, the system can dynamically adjust the output timing of the serial data signal relative to the reference clock, achieving flexible timing control while maintaining a relatively simple overall structure.
2Adaptability or versatility
If multiple clock signals with different phases are generated, then the output timing can be precisely adjusted, but the device complexity increases
Solution Approach 1:
The circuit generates multiple clock signals with periodic phase differences (0°, 90°, 180°, 270°) from a single reference clock signal. This periodic phase structure allows the conversion circuit to select appropriate timing positions systematically, providing flexible timing adjustment capability while using a regular, manageable clock generation approach rather than requiring completely independent complex clock sources.
3Measurement precision
If timing adjustment is limited to fixed intervals, then the circuit is simple to control, but the timing alignment accuracy with memory device is insufficient
Solution Approach 1:
The circuit provides different timing adjustment capabilities for different output positions. By using phase-divided clock signals, each bit position in the parallel input can be converted to serial output with precise timing control relative to the reference clock. This local timing quality enhancement allows accurate alignment with memory device requirements while maintaining systematic control through phase selection.
Data Source
AI summary
A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.