Parallel-to-Serial Interface Circuit for Jitter-Resistant Data Output
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Solution Overview
Problem
Existing parallel-to-serial interface circuits face challenges in effectively reducing jitter and distortion in data transmission due to power supply voltage noise and clock signal noise, which affects the reliability of data conversion and transmission.
Innovation Solution
A parallel-to-serial interface circuit is designed with a configuration that includes a parallel-to-serial converter, an equalizer, a differential data generator, and a driver, utilizing separate internal power supply voltages to generate clock signals and data levels, which alternately select and invert data to compensate for distortion and noise, thereby reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate internal power supply voltages are used to generate clock signals, then jitter is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The power supply system is segmented into two separate internal power supply voltages (first internal power supply voltage and second internal power supply voltage) that are supplied to different clock signal generators. This segmentation isolates the noise sources, preventing power supply noise from affecting both clock signals simultaneously, thereby reducing jitter in the parallel-to-serial conversion process while maintaining manageable complexity through modular power supply design.
Solution Approach 2:
Different clock signal generators are provided with different power supply quality characteristics. The first clock signal generator receives the first internal power supply voltage, while the second clock signal generator receives the second internal power supply voltage. This local differentiation ensures that each clock signal is generated with optimized noise characteristics suitable for its specific function in the data transmission system.
2Manufacturing precision
If equalizer and differential data generator are added to compensate for distortion, then data quality is improved, but device complexity increases
Solution Approach 1:
The equalizer performs preliminary distortion compensation on the data signals before they are converted to differential signals by the differential data generator. By addressing distortion issues in advance, before the data enters the more complex differential signaling stage, the system achieves high data conversion precision while managing overall circuit complexity through staged signal processing.
Solution Approach 2:
The equalizer acts as an intermediary component between the parallel-to-serial converter and the differential data generator. It processes the single-ended data signals, compensating for channel distortion and preparing the signals for subsequent differential conversion. This intermediary function improves data quality without requiring the differential data generator to handle both conversion and equalization functions simultaneously.
3Object-affected harmful factors
If multiple clock signal generators with separate power supplies are used, then noise-induced distortion is reduced, but use of energy increases
Solution Approach 1:
The system changes the power supply parameters by providing two separate internal power supply voltages to different clock signal generators. This parameter differentiation allows each clock signal to be generated with optimized noise characteristics, reducing power supply noise coupling and minimizing jitter. The energy consumption increase is minimized by using integrated internal power supply voltages rather than external supplies, and by optimizing the power distribution within the semiconductor device.
Data Source
AI summary
A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.