Parallel Serial Link Fault Detection via Hardware Redundancy
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Solution Overview
Problem
Data transmission systems in industrial control systems face reliability challenges due to the lack of processing capabilities in some I/O devices, necessitating improved fault detection and error correction mechanisms that are independent of software oversight and resource-intensive protocols.
Innovation Solution
A hardware-based serial link fault detection system utilizing parallel serial links to transmit identical communication signals, enabling fault detection and real-time error correction through hardware redundancy, specifically employing a triple modular redundancy architecture and low-level serial communication protocols like RS-232 or RS-485, which minimizes resource usage and meets safety integrity level certifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software oversight and processing protocols (e.g., Foundation Fieldbus) are used to improve transmission reliability, then communication reliability is improved, but processing capabilities and resource consumption increase
Solution Approach 1:
The patent replaces software-based fault detection with a hardware-based solution using parallel serial links and XOR gates. The physical layer redundancy and hardware comparison mechanism eliminate the need for software oversight, providing reliable fault detection without requiring processing capabilities in I/O devices.
Solution Approach 2:
The patent implements fault detection by transmitting duplicate data through parallel serial links and comparing the copies using XOR gates. This copying approach enables hardware-based verification of data integrity without requiring complex processing, as the comparison logic is performed automatically at the physical layer.
2Reliability
If hardware-based fault detection with parallel serial links is implemented, then fault detection capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the communication channel into parallel serial links, allowing independent transmission and fault detection for each link. This segmentation enables targeted fault isolation without requiring complete system redundancy, reducing overall hardware complexity while maintaining reliability.
Solution Approach 2:
The patent combines multiple serial links into a single communication channel at the receiver end, using XOR gates to merge the parallel data streams. This merging approach allows fault detection through comparison while maintaining a simple interface structure that does not significantly increase device complexity.
Data Source
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AI summary
One embodiment describes a fault tolerant transmission system 10 that includes a programmable logic device 15. The programmable logic device 15 includes a first serial port communicatively coupled to a first serial link 40, in which the first serial port receives a first transmission signal from the first serial link, and a second serial port communicatively coupled to a second serial link 42, in which the second serial port receives a second transmission signal from the second serial link. The first serial link and the second serial link are disposed in parallel with each other and communicate over a first single conduit 38, and the first communication signal and the second communication signal are representative of identical information. The programmable logic device 15 further includes circuitry that detects a fault in the first serial link, the second serial link, or both by comparing the first communication signal and the second, and if a fault is detected, determines whether the transmission system 10 can continue operation despite the fault.