Parallel Shift Register Circuit for Faster Read/Write Training Data
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Solution Overview
Problem
Existing data storage circuits face a low data generation speed during read/write training due to the limitations of linear feedback shift register (LFSR) circuits, which generate data at a relatively slow pace.
Innovation Solution
A random data generation circuit utilizing two shift registers and a parallel-to-serial circuit, where each shift register outputs parallel data that is converted into serial data, allowing for at least 2 bits of data to be generated per clock cycle, significantly improving data generation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an LFSR circuit is used to generate training data, then the circuit structure is simple and easy to implement, but the data generation speed is relatively low
Solution Approach 1:
The patent divides the data generation function into multiple parallel shift registers (first shift register and second shift register), each generating data independently. This segmentation allows simultaneous generation of multiple data streams, increasing overall data generation speed while maintaining the simplicity of individual shift register structures.
Solution Approach 2:
The patent transitions from serial data output to parallel data generation by using multiple shift registers operating simultaneously. The parallel-to-serial conversion circuit then transforms this parallel data into the required serial format, adding a dimensional transformation layer that resolves the contradiction between speed and complexity.
2Productivity
If multiple shift registers are used to generate data in parallel, then data generation speed increases, but the circuit complexity increases
Solution Approach 1:
The patent merges the output of multiple parallel shift registers through a parallel-to-serial conversion circuit. This combining approach consolidates the parallel data streams into a single serial output, achieving high data generation speed while managing circuit complexity through functional integration rather than separate output paths.
Solution Approach 2:
The parallel-to-serial conversion circuit serves multiple functions: it collects data from multiple shift registers, manages the parallel-to-serial transformation, and provides a unified serial output. This multi-functionality reduces the need for additional dedicated circuits for each shift register output, thereby controlling overall circuit complexity.
3Productivity
If an LFSR circuit generates 1 bit of data per clock cycle, then the circuit operation is simple, but the training efficiency is low
Solution Approach 1:
The patent prepares multiple data bits in parallel within the shift registers before they are serialized and output. This preliminary parallel preparation of data allows the system to deliver multiple bits of training data in sequence without requiring multiple clock cycles of computation, thereby reducing training time while maintaining simple clocked operation.
Solution Approach 2:
The patent ensures continuous data generation by having multiple shift registers operate in parallel throughout each clock cycle, with the parallel-to-serial conversion continuously transforming the parallel data into serial output. This continuous parallel processing followed by serialization maintains uninterrupted training data supply, improving training efficiency without introducing complex intermittent operations.
Data Source
AI summary
A random data generation circuit includes: a first shift register and a second shift register. The first shift register includes n output ends Q1 to Qn, the second shift register includes n output ends Qn+1 to Q2n, and each of the output ends outputs 1-bit data in a clock cycle of a clock signal; and a parallel-to-serial circuit, coupled to the output ends Q1 to Q2n and configured to convert parallel data output from Q1 to Q2n in a clock cycle into serial data for output. An initial value of the first shift register is different from an initial value of the second shift register. Data may be generated in parallel by using two shift registers, and the parallel data generated by the two shift registers is converted into serial data by using the parallel-to-serial circuit to be output.