Parallel Linear Feed Forward Shift Registers for Digital Signal Processing
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Solution Overview
Problem
Existing digital signal processing methods, particularly in railway communication systems using the Eurobalise protocol, face inefficiencies in processing times due to differences in clock requirements for long and short telegrams, necessitating a faster method to decode digital signals.
Innovation Solution
Connecting multiple linear feed forward shift registers in parallel to divide and process input values, allowing for the generation of output signals in a manner that reduces the overall clock requirements for processing digital signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single linear feed forward shift register is used for serial processing, then the device complexity is low, but the processing speed is limited and cannot handle large numbers of input values efficiently
Solution Approach 1:
The input data is divided into multiple segments that are processed simultaneously by multiple shift registers. Each shift register handles a portion of the input values in parallel, thereby increasing the overall processing capacity and speed without requiring a single complex register
2Productivity
If multiple linear feed forward shift registers are used for parallel processing, then the processing speed increases and can handle large numbers of input values, but the device complexity increases
Solution Approach 1:
Multiple shift registers are combined in a structured parallel configuration where they share common control signals and output aggregation logic. This merging approach allows parallel processing of multiple input values while reducing the overall device complexity compared to completely independent register systems
3Loss of time
If serial processing is used, then the device complexity is low, but the processing time increases for large numbers of input values
Solution Approach 1:
The processing approach transitions from a one-dimensional serial sequence to a two-dimensional parallel structure. Multiple shift registers operate simultaneously on different segments of input data, effectively adding a temporal parallelism dimension that reduces total processing time while maintaining manageable device complexity
Data Source
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AI summary
A digital signal processing apparatus of the present disclosure includes: a grouping unit configured to generate G number of input signal groups by dividing input signals, in which N number of input values are sequentially connected, into G number of groups; G number of linear feed forward shift registers into which the input signal groups are input, respectively, the G number of linear feed forward shift registers being connected in parallel to one another; and an output unit configured to receive output values of the G number of linear feed forward shift registers and couple the output values to generate output signals in which N number of output values are sequentially connected.